From patchwork Thu Sep 3 12:27:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 249033 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp551869ilg; Thu, 3 Sep 2020 08:11:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwhIZS0gLS5J9HqrnE79lDhYo3xHc/uy064+s2fYsTMQz/Fzw2nWGisUNaNqw6cv5BhfMG9 X-Received: by 2002:a17:906:850:: with SMTP id f16mr2546141ejd.447.1599145912442; Thu, 03 Sep 2020 08:11:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599145912; cv=none; d=google.com; s=arc-20160816; b=BlGaGGsxJHOi3xvvUgWmg/SQ1ao4tbYeDYrpskO7TJgCekwlA/JTll+QezTQru8RGU EVaN5U/qoWsfINEmz/+36HTRdKUJ4Ox9wYwHpKDVUjyCupEAZ/Jz9nfzKtJzZU4teaBx bdyfVSccQheMDUh7IGPYZo17uqxQ24kAmHSXBFAhqyO1q08jj3wy/3c0ZinxmVOufiZz vJglnt6dLUVAooVl/CMY4h+VR88QVkHd2CXWzUVZtqbnaM2QqcNC7g4deX9mYOsH83lv LYa7lRP65c6xdacswB2yoEt4IgeCPGxIWpX8L2jIkZu9Y0sFttdBIsRYc7rBuTCxyYuX DWBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=RxPo8ssE9+I6AEevKntUpzTA/olB0RzJ65L3WwS7Qt8=; b=H70xz0RMTTTwUwQi66tYeJBZ6fFZ8MkyU3N9MbBNVUSnk+fDiVPgSyWBkMCFTmQJaC Vm1x7pyhbH/dxXHBq6MZdcHm/NNe2ppVhf78D+kJIXFwyf1FwdIsCA48AlpSQ9mqkq8a uOv0B3tNGjJ9akh3/e8jM0LarhQn6+akiZQOgFIlICi/C8Ar2a3he9rDWFJP6BPhEXcn UiqzbBMGyKTCrznpv8sz2Tq10gH/Q/iEv/CXtY/QGWqh3SsKlQp+1vf76gX+X2uzxvNl SbOQyEeZpGhlAMKzdI5NWR4cXKZBbbJs2pgO3urK9naCnszshd1URaw+s3zdnq192y60 R4jw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id f14si2039050ejq.98.2020.09.03.08.11.52; Thu, 03 Sep 2020 08:11:52 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728756AbgICM2p (ORCPT + 6 others); Thu, 3 Sep 2020 08:28:45 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:48950 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728565AbgICM2k (ORCPT ); Thu, 3 Sep 2020 08:28:40 -0400 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 7C657E04B63EC1F09FCD; Thu, 3 Sep 2020 20:28:32 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.487.0; Thu, 3 Sep 2020 20:28:24 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , linux-arm-kernel , devicetree , linux-kernel CC: Zhen Lei , Kefeng Wang Subject: [PATCH 3/3] ARM: dts: add SD5203 dts Date: Thu, 3 Sep 2020 20:27:34 +0800 Message-ID: <20200903122734.2369-4-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200903122734.2369-1-thunder.leizhen@huawei.com> References: <20200903122734.2369-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kefeng Wang Add sd5203.dts for Hisilicon SD5203 SoC platform. Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/sd5203.dts | 90 ++++++++++++++++++++++++++++++++++++ 2 files changed, 92 insertions(+) create mode 100644 arch/arm/boot/dts/sd5203.dts -- 2.26.0.106.g9fadedd diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae..1d1262df5c55 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -357,6 +357,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \ mps2-an399.dtb dtb-$(CONFIG_ARCH_MOXART) += \ moxart-uc7112lx.dtb +dtb-$(CONFIG_ARCH_SD5203) += \ + sd5203.dtb dtb-$(CONFIG_SOC_IMX1) += \ imx1-ads.dtb \ imx1-apf9328.dtb diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts new file mode 100644 index 000000000000..99da46072f72 --- /dev/null +++ b/arch/arm/boot/dts/sd5203.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020 Hisilicon Limited. + * + * DTS file for Hisilicon SD5203 Board + */ + +/dts-v1/; + +/ { + model = "Hisilicon SD5203"; + compatible = "hisilicon,sd5203"; + interrupt-parent = <&vic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; + }; + + aliases { + serial0 = &uart0; + }; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + + memory@30000000 { + device_type = "memory"; + reg = <0x30000000 0x8000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + vic: interrupt-controller@10130000 { + compatible = "hisilicon,sd5203-vic"; + reg = <0x10130000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + refclk125mhz: refclk125mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + timer0: timer@16002000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16002000 0x1000>; + interrupts = <4>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + timer1: timer@16003000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16003000 0x1000>; + interrupts = <5>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + uart0: serial@1600D000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600D000 0x1000>; + bus_id = "uart0"; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + reg-shift = <2>; + interrupts = <17>; + }; + + uart1: serial@1600C000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600C000 0x1000>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + reg-shift = <2>; + interrupts = <16>; + status = "disabled"; + }; + }; +};