From patchwork Thu Sep 3 12:05:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 249002 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp385420ilg; Thu, 3 Sep 2020 05:12:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy48HZye+ptACXZpzL2jGb/JI8zVsbq/5INy3UhA5mGUAGMQZ9Jkvt+mbLjbGJtJ3mqW4tG X-Received: by 2002:a17:906:a141:: with SMTP id bu1mr1773011ejb.303.1599135151327; Thu, 03 Sep 2020 05:12:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599135151; cv=none; d=google.com; s=arc-20160816; b=avKPMF+bktCpCvCwQahP44iKul1qdhqRiSF/m5RBFPpYBKuQF8v9GhJQMBa1GE0iPi pZZNGffyOLa+UIegPkyNL3PvEY6/XIq5hShm9d+WmDmliwRSy0WYtruK/wKYesjcOxoF Je36/k/VO6W3ETFENun+rgoYbrpSgZqm7URew8lvhQXRBcrWRyGGubsKvRGnlA1Kffgo t2bGlpGPe6BpR27HXatfI3WH6r+B57JsRUtgp3PbFats9YRNlTloh83USIpty4vC5GY8 D8im5X0Ei27gcHhTHlUajkw4yY5IWpodIYqPygb4a0Td9XUbvHxSEMS/u0XFSEtO1IVt km2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=6MW6xuUFdFupg6cBbkQHmmQE+y5gGuZiqi9ePNIY7nw=; b=Ed9U29dyXVpB5OtmqtnLJlEB1EShlEsYkK4xrV3FeqQsrRv01igWGrrvJgS5M9bHGK LyOH/vlffwJyinD57mvG/wPkLBVwV3U3Ht3qbWJwbtNF4jfbxjQMjO8tX65sgmHAtKKg VPBy27Q8xHOm9km51l8jvY9sct4lSsjDcKScSe3Dq/GM6LSenlKNh0p3sUj793VKkEwc tw7AEmPRmIrZWNUr2OQy2RMa+j7SUmYwYS6SpeGy8GI/buStuKiyU0/yWZquMDiQXAMb 09vdRe5f/d9H9+lM5Pg+xKqcn/utrHusrUS6dahrR2WuzVLdiERqJvd1UqerSIofcvT3 zlFA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y10si1636903edi.9.2020.09.03.05.12.31; Thu, 03 Sep 2020 05:12:31 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728800AbgICMJm (ORCPT + 6 others); Thu, 3 Sep 2020 08:09:42 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:37492 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728810AbgICMFw (ORCPT ); Thu, 3 Sep 2020 08:05:52 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 6FDF925D277F9FD9C604; Thu, 3 Sep 2020 20:05:27 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Thu, 3 Sep 2020 20:05:19 +0800 From: Zhen Lei To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , devicetree , linux-kernel CC: Zhen Lei , Kefeng Wang Subject: [PATCH 1/2] dt-bindings: interrupt-controller: add Hisilicon SD5203 vector interrupt controller Date: Thu, 3 Sep 2020 20:05:03 +0800 Message-ID: <20200903120504.2308-2-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200903120504.2308-1-thunder.leizhen@huawei.com> References: <20200903120504.2308-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings for the Hisilicon SD5203 vector interrupt controller. Signed-off-by: Zhen Lei --- .../hisilicon,sd5203-vic.txt | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt -- 2.26.0.106.g9fadedd diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt new file mode 100644 index 000000000000..a08292e868b0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt @@ -0,0 +1,27 @@ +Hisilicon SD5203 vector interrupt controller (VIC) + +Hisilicon SD5203 VIC based on Synopsys DesignWare APB interrupt controller, but +there's something special: +1. The maximum number of irqs supported is 32. The registers ENABLE, MASK and + FINALSTATUS are 32 bits. +2. There is only one VIC, it's used as primary interrupt controller. + +Required properties: +- compatible: shall be "hisilicon,sd5203-vic" +- reg: physical base address of the controller and length of memory mapped + region starting with ENABLE_LOW register +- interrupt-controller: identifies the node as an interrupt controller +- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1 + +The interrupt sources map to the corresponding bits in the interrupt +registers, i.e. +- 0 maps to bit 0 of low interrupts, +- 1 maps to bit 1 of low interrupts, + +Example: + vic: interrupt-controller@10130000 { + compatible = "hisilicon,sd5203-vic"; + reg = <0x10130000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + };