From patchwork Fri Aug 28 16:47:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 253230 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 187D1C433E7 for ; Fri, 28 Aug 2020 16:50:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ECA3A20738 for ; Fri, 28 Aug 2020 16:50:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1598633433; bh=Cgxn33agiAyp87HeECnZVMhxGfb2+DrRvu3F+O4k4xU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=zmxDfAdh2UGExfHVpg2x60+8s1byHVI9VRBbD0LVzVFy7RwYjk6c6Z6cAeGprtKlw kf2aKb7vwOgUdy9ks6h08IhoSHROKaUiPOIMb1+OiBB82dy5DlewT090a01Mmi4jhA +fDXfUnovu3h0DKFplQJdSSOMEtclt0v7zM1jdfc= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728434AbgH1Qu1 (ORCPT ); Fri, 28 Aug 2020 12:50:27 -0400 Received: from mail.kernel.org ([198.145.29.99]:44590 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728282AbgH1QuX (ORCPT ); Fri, 28 Aug 2020 12:50:23 -0400 Received: from kozik-lap.mshome.net (unknown [194.230.155.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A1DC820C56; Fri, 28 Aug 2020 16:50:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1598633422; bh=Cgxn33agiAyp87HeECnZVMhxGfb2+DrRvu3F+O4k4xU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XMecWnAgOXRnqFZguFNZP++EQZeOKRRS5Pe+Zk8bSrrUsCjXle74AErcIw7+ZWsoF ervXUHTa8lWgRKeZ7FLmxkSRfE3N+9xeZjqe8jJFQWe4m2Vyjhj0irN8yl5C6TFrFF 3KKcfKi81CTMl2bK/i/TBBzarDVDs/FzlFRWjCSY= From: Krzysztof Kozlowski To: Lee Jones , Rob Herring , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Anson Huang , Matti Vaittinen , Han Xu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 15/19] arm64: dts: imx8mq-phanbell: Align pin configuration group names with schema Date: Fri, 28 Aug 2020 18:47:46 +0200 Message-Id: <20200828164750.10377-16-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200828164750.10377-1-krzk@kernel.org> References: <20200828164750.10377-1-krzk@kernel.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Device tree schema expects pin configuration groups to end with 'grp' suffix, otherwise dtbs_check complain with a warning like: ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts index 3f541ddf0768..d6d3a3d5abc3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts @@ -365,7 +365,7 @@ >; }; - pinctrl_pmic: pmicirq { + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 >; @@ -395,7 +395,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 @@ -412,7 +412,7 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 @@ -429,7 +429,7 @@ >; }; - pinctrl_usdhc2_gpio: usdhc2grpgpio { + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 @@ -448,7 +448,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 @@ -460,7 +460,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7