From patchwork Fri Aug 28 16:47:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 253232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E1ADC433E6 for ; Fri, 28 Aug 2020 16:50:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7F57820848 for ; Fri, 28 Aug 2020 16:50:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1598633412; bh=+6fsx9inRaN4fvWlXSXEShmnP49N2TqHhDeCV/p1ZRQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=nAXjrCrJmLnKU7RFnGH+7O66oFt2nOMdA00Cuoc5L8plWM4JCPnvYRQVo/OQD8sjw DUXswLors3lNzvpWog4fyCy/EyGA5hJ4FPgIejngwM7TqDVbaV/IqX9KpvhpdwVB+P eiptFrylKt1x5wBZPWfeEHUz84X4HdR5fLaxXPaQ= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727842AbgH1QuK (ORCPT ); Fri, 28 Aug 2020 12:50:10 -0400 Received: from mail.kernel.org ([198.145.29.99]:44316 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728516AbgH1QuJ (ORCPT ); Fri, 28 Aug 2020 12:50:09 -0400 Received: from kozik-lap.mshome.net (unknown [194.230.155.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id BAF0220848; Fri, 28 Aug 2020 16:49:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1598633408; bh=+6fsx9inRaN4fvWlXSXEShmnP49N2TqHhDeCV/p1ZRQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EY3QSrQXRi9zJVZlyJEvs+YDS6UqgmteCDMEekNQKVHRrRxyiyZlqBiXRutVL7VMy G+Px4/J18JqSBxqCkRTjTriTHkxbXgyWdoAlLHbfipT7EE40O4Q6YmbkhZp5yQBcla +3RA/L0rL8jfHm9KGWfx71GLSyF9/eccCA1DYwm8= From: Krzysztof Kozlowski To: Lee Jones , Rob Herring , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Anson Huang , Matti Vaittinen , Han Xu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 14/19] arm64: dts: imx8mq-librem5-devkit: Align pin configuration group names with schema Date: Fri, 28 Aug 2020 18:47:45 +0200 Message-Id: <20200828164750.10377-15-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200828164750.10377-1-krzk@kernel.org> References: <20200828164750.10377-1-krzk@kernel.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Device tree schema expects pin configuration groups to end with 'grp' suffix, otherwise dtbs_check complain with a warning like: ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/freescale/imx8mq-librem5-devkit.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index 6900ac274f5b..377591a0e6e9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -734,7 +734,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd @@ -751,7 +751,7 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf @@ -768,13 +768,13 @@ >; }; - pinctrl_usdhc2_pwr: usdhc2grppwr { + pinctrl_usdhc2_pwr: usdhc2pwrgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 >; }; - pinctrl_usdhc2_gpio: usdhc2grpgpio { + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */ >; @@ -791,7 +791,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd @@ -802,7 +802,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf