From patchwork Fri Aug 28 16:47:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 253234 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A71CC433E2 for ; Fri, 28 Aug 2020 16:49:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EF8B420EDD for ; Fri, 28 Aug 2020 16:49:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1598633385; bh=FkLjw7Jcs543SiKoNIN05bHQA4tIrsY4ElZISGC6hZE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=XzQxYCcbj7tQEwktMI/wuArUTW8QkEXLvK2Fs3HqEivc+47kNwEvddmLNQ2p6kidl wusS98aJHEGEbuH3i9H57QoOldHXO5DSPj9ZPGv6Brh0uqWr7A/00tPKCJTf6rLgDE al6nx1xQnxWOkc4YVxq4g4nOICsL5SG7nf9uQobw= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728451AbgH1Qtn (ORCPT ); Fri, 28 Aug 2020 12:49:43 -0400 Received: from mail.kernel.org ([198.145.29.99]:43606 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728446AbgH1Qtk (ORCPT ); Fri, 28 Aug 2020 12:49:40 -0400 Received: from kozik-lap.mshome.net (unknown [194.230.155.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 97B9720B80; Fri, 28 Aug 2020 16:49:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1598633379; bh=FkLjw7Jcs543SiKoNIN05bHQA4tIrsY4ElZISGC6hZE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rM1dwyRgJ3KIP0QWWY77IMjSthExMTWxWT5YYeEBwDfTvME0q5IyMTZCTJ8MgVZDB 8+CKUzWnucoUCyZsoBFjl+D5S8PtxnCGVBCvDP4fBOHTWyPOv/YZBSAcA+bJFBBENz JXBpltlA5wgx+bDQTSqZsYcWFqAR2eMbGM2s1S50= From: Krzysztof Kozlowski To: Lee Jones , Rob Herring , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Anson Huang , Matti Vaittinen , Han Xu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 09/19] arm64: dts: imx8mm-evk: Align pin configuration group names with schema Date: Fri, 28 Aug 2020 18:47:40 +0200 Message-Id: <20200828164750.10377-10-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200828164750.10377-1-krzk@kernel.org> References: <20200828164750.10377-1-krzk@kernel.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Device tree schema expects pin configuration groups to end with 'grp' suffix, otherwise dtbs_check complain with a warning like: ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index 0115f07bbc9d..207dc8de3145 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -423,13 +423,13 @@ >; }; - pinctrl_pmic: pmicirq { + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 >; }; - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 >; @@ -457,7 +457,7 @@ >; }; - pinctrl_usdhc2_gpio: usdhc2grpgpio { + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 >; @@ -475,7 +475,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 @@ -487,7 +487,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 @@ -515,7 +515,7 @@ >; }; - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 @@ -531,7 +531,7 @@ >; }; - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6