From patchwork Wed Jul 29 15:43:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 247253 Delivered-To: patch@linaro.org Received: by 2002:a50:110d:0:0:0:0:0 with SMTP id e13csp1214373eck; Wed, 29 Jul 2020 08:44:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJycKSTzzAQkuxGRJEK2d0RD7Srq89LMos9lqbiu6eJ18UObNLzlOwMwo2coFK4VHjEiPuUV X-Received: by 2002:a17:906:7044:: with SMTP id r4mr1745791ejj.440.1596037459610; Wed, 29 Jul 2020 08:44:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596037459; cv=none; d=google.com; s=arc-20160816; b=PtvU4RoBIbKAlz9KWT2ymbynYVEHr0kR4jPOerhTt5xdEc1ZkyrH4En+s2MI2Vpl+w 10GQLTBA6hXgkifwpgOIIJ5w5nkGPddGfsRFCYX1KybivuROSRtK+melz2BmVs93KNas FJttk/ueSekx94sJ3CQ+/h3CSRcAmFWFZI2C1DB/BfmSFWdXUb0DlTcLuElDJfPNhh/w 1Yv8Z7Akic4qODGe6CBF0GjZZHSAAAmfXMScm6W7Rp4xyyZhsFgEZgLMkmFjnCUmcPsc M4yuLPqxgB87WFx9Dc3UGrBnpv7A0D1dc3Y0nVWIK5wB6K4QkXYm3cC5FLt+/Odet8Kh 9BTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=CQIn+VEpnEWmSg9hS5AE3VgFC5CX71fT+x9MqwA/nSI=; b=dfsEoTK1aEopBekd6rt8GPzL4exeYteqpBlVEcA6l7qELpKOs/SWouH8P4X+myEt9D 2QDlH+JxApZus/GU06H6yy5iKnIS0McucQhT9gBp2+mVjGGxxpnmFzM9OVhFled3RPtI qMJevCS/2CGGdy5i9eeypqU9XH/fYfpX5z5y5Qn+d5F8Av1c8mfDEQtbs3PoJVa3kBZ1 2cJeHWWFZqIwc4WzERERbafwVYmUQwinp6bNoRMGv/cN2jf3rmyAOZFZarrxHyuy9OOg 4G/s1ZA+bzbCVm1hmsQ1ewex92OicT2A0Nc9xtb2KuvwiZvUbY/gsEhiaA7i8FomfqHs yWGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=Eo+0w9c4; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id g6si1365243ejr.426.2020.07.29.08.44.19; Wed, 29 Jul 2020 08:44:19 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=Eo+0w9c4; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726956AbgG2PoM (ORCPT + 6 others); Wed, 29 Jul 2020 11:44:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726913AbgG2PoJ (ORCPT ); Wed, 29 Jul 2020 11:44:09 -0400 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4332FC0619D2 for ; Wed, 29 Jul 2020 08:44:09 -0700 (PDT) Received: by mail-wr1-x441.google.com with SMTP id r12so22044627wrj.13 for ; Wed, 29 Jul 2020 08:44:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CQIn+VEpnEWmSg9hS5AE3VgFC5CX71fT+x9MqwA/nSI=; b=Eo+0w9c4wPP7x+MiwaxTzJX484Ai6UmktMd8hl2Q5Eu7JdW4RcKGROLAIeJ5MoIQV7 SZcw9L4eFS3ufCY7FdWL6qdbbUhqqMv6kq8e+lMtk0B8HsVV1NzGj9IQHgXOVNmfbF0M OUJ/zIkQq+hDQd4iUqTxiwsL5SAiAApARsYsD74qqaC4Y+obzj0AoV4o1diNM3v7SLv4 BVSrUDX06j9FXxvYq2WM+PBBHSvDwOYZZcNy67cs4+O7DWffIQ0YR4FXK/eGvUPdkjEu PtXZLqU9kaZ+ojo7qYMIcESGpKDoKrMkwi3d7AcS3h+7Fho57bOiamNQkQVRChsYf6p5 JI+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CQIn+VEpnEWmSg9hS5AE3VgFC5CX71fT+x9MqwA/nSI=; b=f/nqOohWeDbslyjcz76T4p8QW/hp/jH3DDfZzEJyRjJjAbFeR/6JM3/WCkQ5dqxVwi IbI/ROgYeyM+SBGkZ2lNwiMfU/IbGWgUOHVl3SPi8MVOyYVhxRk6f7MKwZi35x8mBU0h ohH8RSiB0sI+EeRWYwWbFTOxn3YlBw67lN5Cp00JDh4Ybu3d6CD4NGfvAnUpjVjFYs8V H81UnyG5M8H6t5zfBA9WNdnXhKAczLNFQ3Kw+ZQxK/E/ZFvh/dQxfA92hYGvHTg1oK4h zwvk4UzuT8xpjOKp913mCya4B8epdclJFy355GTofBTQ1aaCSaZfgFtv8VvS2VXBryb1 /stQ== X-Gm-Message-State: AOAM5301YSM5xIlvo/NvzvlfiqPU0D2vC/C5+J5dQmEvqoCkc/Vgt4Si tGYNBi/CbpZYZTlSinWPDFXUfQ== X-Received: by 2002:adf:de8d:: with SMTP id w13mr29665660wrl.129.1596037447519; Wed, 29 Jul 2020 08:44:07 -0700 (PDT) Received: from starbuck.baylibre.local (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.googlemail.com with ESMTPSA id a134sm6526030wmd.17.2020.07.29.08.44.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jul 2020 08:44:06 -0700 (PDT) From: Jerome Brunet To: Neil Armstrong , linux-clk@vger.kernel.org Cc: Jerome Brunet , Kevin Hilman , linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] clk: meson: add sclk-ws driver Date: Wed, 29 Jul 2020 17:43:57 +0200 Message-Id: <20200729154359.1983085-2-jbrunet@baylibre.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200729154359.1983085-1-jbrunet@baylibre.com> References: <20200729154359.1983085-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-Patchwork-Bot: notify Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This is yet another simple but odd driver for the audio block of the g12a and sm1 SoC families. For TDMOUT's sclk to be properly inverted, bit 29 of AUDIO_CLK_TDMOUT_x_CTRL should be the inverse of bit 28. IOW bit28 == !bit29 at all times This setting is automatically applied on axg and the manual setting was added on g12a. Signed-off-by: Jerome Brunet --- drivers/clk/meson/clk-phase.c | 56 +++++++++++++++++++++++++++++++++++ drivers/clk/meson/clk-phase.h | 6 ++++ 2 files changed, 62 insertions(+) -- 2.25.4 diff --git a/drivers/clk/meson/clk-phase.c b/drivers/clk/meson/clk-phase.c index fe22e171121a..a6763439f7d2 100644 --- a/drivers/clk/meson/clk-phase.c +++ b/drivers/clk/meson/clk-phase.c @@ -125,6 +125,62 @@ const struct clk_ops meson_clk_triphase_ops = { }; EXPORT_SYMBOL_GPL(meson_clk_triphase_ops); +/* + * This is a special clock for the audio controller. + * This drive a bit clock inverter for which the + * opposite value of the inverter bit needs to be manually + * set into another bit + */ +static inline struct meson_sclk_ws_inv_data * +meson_sclk_ws_inv_data(struct clk_regmap *clk) +{ + return (struct meson_sclk_ws_inv_data *)clk->data; +} + +static int meson_sclk_ws_inv_sync(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_sclk_ws_inv_data *tph = meson_sclk_ws_inv_data(clk); + unsigned int val; + + /* Get phase and sync the inverted value to ws */ + val = meson_parm_read(clk->map, &tph->ph); + meson_parm_write(clk->map, &tph->ws, val ? 0 : 1); + + return 0; +} + +static int meson_sclk_ws_inv_get_phase(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_sclk_ws_inv_data *tph = meson_sclk_ws_inv_data(clk); + unsigned int val; + + val = meson_parm_read(clk->map, &tph->ph); + + return meson_clk_degrees_from_val(val, tph->ph.width); +} + +static int meson_sclk_ws_inv_set_phase(struct clk_hw *hw, int degrees) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_sclk_ws_inv_data *tph = meson_sclk_ws_inv_data(clk); + unsigned int val; + + val = meson_clk_degrees_to_val(degrees, tph->ph.width); + meson_parm_write(clk->map, &tph->ph, val); + meson_parm_write(clk->map, &tph->ws, val ? 0 : 1); + return 0; +} + +const struct clk_ops meson_sclk_ws_inv_ops = { + .init = meson_sclk_ws_inv_sync, + .get_phase = meson_sclk_ws_inv_get_phase, + .set_phase = meson_sclk_ws_inv_set_phase, +}; +EXPORT_SYMBOL_GPL(meson_sclk_ws_inv_ops); + + MODULE_DESCRIPTION("Amlogic phase driver"); MODULE_AUTHOR("Jerome Brunet "); MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/meson/clk-phase.h b/drivers/clk/meson/clk-phase.h index 5579f9ced142..b637b9b227bc 100644 --- a/drivers/clk/meson/clk-phase.h +++ b/drivers/clk/meson/clk-phase.h @@ -20,7 +20,13 @@ struct meson_clk_triphase_data { struct parm ph2; }; +struct meson_sclk_ws_inv_data { + struct parm ph; + struct parm ws; +}; + extern const struct clk_ops meson_clk_phase_ops; extern const struct clk_ops meson_clk_triphase_ops; +extern const struct clk_ops meson_sclk_ws_inv_ops; #endif /* __MESON_CLK_PHASE_H */