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[23.128.96.18]) by mx.google.com with ESMTP id b7si2252324edq.546.2020.07.23.08.26.55; Thu, 23 Jul 2020 08:26:56 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ithbTwaA; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729531AbgGWP0y (ORCPT + 6 others); Thu, 23 Jul 2020 11:26:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729471AbgGWP0y (ORCPT ); Thu, 23 Jul 2020 11:26:54 -0400 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC8D7C0619E2 for ; Thu, 23 Jul 2020 08:26:53 -0700 (PDT) Received: by mail-wr1-x441.google.com with SMTP id r12so5533823wrj.13 for ; Thu, 23 Jul 2020 08:26:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zeGJhn4QDCv7nHVcfBN1kEkOyeVk60ndJ+Wwf4G4XD8=; b=ithbTwaAxz5gEQyqNKS5Bgr8alt7QgnzfxZxjJOD22GNv7bw/z7+Mv9FziFhf2osFN M7l4Ta1TEBAqu5jbhVnArS15n2TW9DfPcJG4y5J/4Gx5ghIPSpbqVFIx0r+T4OJd4DLy AhKe6M5iim0KX1Ogub076YX1Y1RBT3a1rc4rNrX8dQ8rm6nZgDnUmxCx6On/Y/dSPdfc ZP12IT21nm+RRXaXPglA/+vvVtGAsnAJCLg5LXgTKNtsnadDiuWfWw9ge81/zORa+knG h+CrlR0F363lJ2GWrNQ+b82imr5aRHehlunZtZK8ywPVRKwR86/YDHmlQzkiVBLw11MG vEEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zeGJhn4QDCv7nHVcfBN1kEkOyeVk60ndJ+Wwf4G4XD8=; b=UNzPxolzLIQp1aKbyM2fp9Iu+ZH1G8PAsAmlCpPwSpIs1uqYPKlsw3Ah5i/b+wHY+B rFhK7YvHBNjx/wT7ZdxZRYzXgI6rKKxsATkPYZfeOCAms27cOZdWs51yRqvgC8wiyOgq MhwdGZqvJdS1zKpW7YhXRCm3jIKQFaRW04qhKyUwGQuY4j5otjnrDkV7ERa/GdMGlJ7v w4DDK4JuaE1dvyc9tj8G+3frOKN1m9N/Dsh2Z8dyd7bCLvl1S7xXvenLNdnpUnEj5PP1 mZxNZ/DyCvo6Slquc2nSUWNTI2R/Pkct0i08iTHxqMewHXOXeeklzC+wbBYubUlrBl2e tj8w== X-Gm-Message-State: AOAM531pAw5gESwbOzgzCah1RS72+McKl0j1285HFDJh2mpkEoKCkQhn PAZvbunm/uQV077vM9Tzt0pAHUSdUrgLjA== X-Received: by 2002:adf:d084:: with SMTP id y4mr4383828wrh.161.1595518012378; Thu, 23 Jul 2020 08:26:52 -0700 (PDT) Received: from mai.imgcgcw.net ([2a01:e34:ed2f:f020:dca7:8d30:33fa:daac]) by smtp.gmail.com with ESMTPSA id g145sm5963491wmg.23.2020.07.23.08.26.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2020 08:26:51 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: Alexandre Belloni , Rob Herring , Lee Jones , Rob Herring , Nicolas Ferre , Ludovic Desroches , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Microchip (AT91) SoC support), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 01/16] dt-bindings: atmel-tcb: convert bindings to json-schema Date: Thu, 23 Jul 2020 17:26:21 +0200 Message-Id: <20200723152639.639771-1-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <1b1122f4-bce9-f349-e602-ed8e14cbb501@linaro.org> References: <1b1122f4-bce9-f349-e602-ed8e14cbb501@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Alexandre Belloni Convert Atmel Timer Counter Blocks bindings to DT schema format using json-schema. Also move it out of mfd as it is not and has never been related to mfd. Signed-off-by: Alexandre Belloni Reviewed-by: Rob Herring Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20200710230813.1005150-2-alexandre.belloni@bootlin.com --- .../devicetree/bindings/mfd/atmel-tcb.txt | 56 -------- .../soc/microchip/atmel,at91rm9200-tcb.yaml | 131 ++++++++++++++++++ 2 files changed, 131 insertions(+), 56 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-tcb.txt create mode 100644 Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml -- 2.25.1 Acked-by: Lee Jones diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt deleted file mode 100644 index c4a83e364cb6..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt +++ /dev/null @@ -1,56 +0,0 @@ -* Device tree bindings for Atmel Timer Counter Blocks -- compatible: Should be "atmel,-tcb", "simple-mfd", "syscon". - can be "at91rm9200" or "at91sam9x5" -- reg: Should contain registers location and length -- #address-cells: has to be 1 -- #size-cells: has to be 0 -- interrupts: Should contain all interrupts for the TC block - Note that you can specify several interrupt cells if the TC - block has one interrupt per channel. -- clock-names: tuple listing input clock names. - Required elements: "t0_clk", "slow_clk" - Optional elements: "t1_clk", "t2_clk" -- clocks: phandles to input clocks. - -The TCB can expose multiple subdevices: - * a timer - - compatible: Should be "atmel,tcb-timer" - - reg: Should contain the TCB channels to be used. If the - counter width is 16 bits (at91rm9200-tcb), two consecutive - channels are needed. Else, only one channel will be used. - -Examples: - -One interrupt per TC block: - tcb0: timer@fff7c000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfff7c000 0x100>; - interrupts = <18 4>; - clocks = <&tcb0_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - -One interrupt per TC channel in a TC block: - tcb1: timer@fffdc000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfffdc000 0x100>; - interrupts = <26 4>, <27 4>, <28 4>; - clocks = <&tcb1_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - diff --git a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml new file mode 100644 index 000000000000..9d680e0b9109 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Atmel Timer Counter Block + +maintainers: + - Alexandre Belloni + +description: | + The Atmel (now Microchip) SoCs have timers named Timer Counter Block. Each + timer has three channels with two counters each. + +properties: + compatible: + items: + - enum: + - atmel,at91rm9200-tcb + - atmel,at91sam9x5-tcb + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + + interrupts: + description: + List of interrupts. One interrupt per TCB channel if available or one + interrupt for the TC block + minItems: 1 + maxItems: 3 + + clock-names: + description: + List of clock names. Always includes t0_clk and slow clk. Also includes + t1_clk and t2_clk if a clock per channel is available. + oneOf: + - items: + - const: t0_clk + - const: slow_clk + - items: + - const: t0_clk + - const: t1_clk + - const: t2_clk + - const: slow_clk + minItems: 2 + maxItems: 4 + + clocks: + minItems: 2 + maxItems: 4 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^timer@[0-2]$": + description: The timer block channels that are used as timers. + type: object + properties: + compatible: + const: atmel,tcb-timer + reg: + description: + List of channels to use for this particular timer. + minItems: 1 + maxItems: 3 + + required: + - compatible + - reg + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + /* One interrupt per TC block: */ + tcb0: timer@fff7c000 { + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfff7c000 0x100>; + interrupts = <18 4>; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + /* One interrupt per TC channel in a TC block: */ + tcb1: timer@fffdc000 { + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffdc000 0x100>; + interrupts = <26 4>, <27 4>, <28 4>; + clocks = <&tcb1_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + };