From patchwork Thu Jun 18 13:06:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Erwan Le Ray X-Patchwork-Id: 191102 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp1405451ilo; Thu, 18 Jun 2020 06:07:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw3oFoulAyJhOlfka3LMc33yaaPQcZQT14TfYCBIRat6A4PvF7/ymE0xstJPukzdWJ6HnVX X-Received: by 2002:a17:907:35c2:: with SMTP id ap2mr3684458ejc.530.1592485643776; Thu, 18 Jun 2020 06:07:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1592485643; cv=none; d=google.com; s=arc-20160816; b=bKBVUn70XYDtkGRBQwTuWjzYn2YakoInpTZf8o6TXSY6MEtuHC6D3vFjGFWQ8k59jm 1A/iSpVdVsiQ3jlpOei1cNl0eS5vpSaY9wxNv15HqHsCBB1CkIj8URytXeW4FGuiihY9 pPOYSlB/KCqsWenNvVenq/5X0Zhu4bs39iaukYUnjcRErEEzZQSp97jYjyrP2SY7GDMb XCMyXWkz1EohOu3+EUAMBLi2z4yFX7SdlY7rLldS5P6N5iP5sx3OdiYSVGsszJi1pYdO XAOVg0dIax19eQQIF00HFlV2xn4U/a2dOjYHQGG9wTTcLViWnlGAsks60QS2Wcy13Uoz au3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=5XU/0J3RAI8AZsj9EUAZG/2xnH7KRcguIz1gSCUQgL8=; b=y4a7IRVzMlSNo2w4IQb3uYMpm2g+dMfUmyBtv2GAqP0sFW0NnEPIM2dkaEO83GVEOi Y8EJWvkhjfgTuHm0cOqEkd1Ya3irLa27hFChD2Tvs8IsB1y8vz1Wngm5G7u12IHkbhJu kAb4ibDtf1yGYWselFTJc7d5X/MABAL3IOayJPSn7E5hENLfAaAknAZKXkFAbI59T/Gl pvt9z6i1O/2EJ1X3+8EirQbl3AXZ3tj2CB+3ZbjinsOFgrQNNqBDUdjVz8XxCBooOB6q Vk7S7ZKd02RBDdJymTSL/DWpJYDbJpSElRwYZZj5wPs6DxGLjbWzFG2/QYdFf/vnTLGt nqlw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=Qk4+YYl8; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=st.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id d18si1921810edv.51.2020.06.18.06.07.23; Thu, 18 Jun 2020 06:07:23 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=Qk4+YYl8; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=st.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725953AbgFRNHS (ORCPT + 6 others); Thu, 18 Jun 2020 09:07:18 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:12542 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730078AbgFRNHR (ORCPT ); Thu, 18 Jun 2020 09:07:17 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 05ID4TDA002369; Thu, 18 Jun 2020 15:07:03 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=5XU/0J3RAI8AZsj9EUAZG/2xnH7KRcguIz1gSCUQgL8=; b=Qk4+YYl8GlgAHbuzKtdbXHneDZTRQFNa5antsevYD8QYI4GF/oo1BuJkuqvm/AmvpFS4 QoT9nIXQaIAK3iw1sw/PAqfaF4o440QgpTwIQzoUees9zH38ExEWZ6LOnHN6liQJFDMH X3QviWkhD77oYqlQaT0CRpHaNWx+yG5V+gxtHQy0RHfPS93jro+8LQ3xyHT/jAkMIFuM aEbkYfQYoQDNiA2T9ZDS5+LMBhIpFI5LvnPOVghRWSg2cZ/iSATzJcAxf0rZmDvlo6nF MuHhtoWJ0+Q+f7RU+z9O2r4x9e1c3vpp4GnWQHdc4lX7ZDfFyFcMkctnw63yT/2VdEhc pw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 31q649k3gk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Jun 2020 15:07:03 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id BF2EC100034; Thu, 18 Jun 2020 15:06:59 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag3node1.st.com [10.75.127.7]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id AC9382AAA9A; Thu, 18 Jun 2020 15:06:59 +0200 (CEST) Received: from localhost (10.75.127.44) by SFHDAG3NODE1.st.com (10.75.127.7) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 18 Jun 2020 15:06:59 +0200 From: Erwan Le Ray To: Maxime Coquelin , Alexandre Torgue , Rob Herring , Mark Rutland CC: , , , , Erwan Le Ray , Fabrice Gasnier Subject: [PATCH v2 1/5] ARM: dts: stm32: add usart2, usart3 and uart7 pins in stm32mp15-pinctrl Date: Thu, 18 Jun 2020 15:06:47 +0200 Message-ID: <20200618130651.29836-2-erwan.leray@st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200618130651.29836-1-erwan.leray@st.com> References: <20200618130651.29836-1-erwan.leray@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG4NODE2.st.com (10.75.127.11) To SFHDAG3NODE1.st.com (10.75.127.7) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216, 18.0.687 definitions=2020-06-18_12:2020-06-18,2020-06-18 signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Adds usart2_pins_c, usart3_pins_b, usart3_pins_c and uart7_pins_c pins configurations in stm32mp15-pinctrl. - usart2_pins_c pins are connected to Bluetooth chip on dk2 board. - usart3_pins_b pins are connected to GPIO expansion connector on evx board. - usart3_pins_c pins are connected to GPIO expansion connector on dkx board. - uart7_pins_c pins are connected to Arduino Uno connector on dkx board. Signed-off-by: Erwan Le Ray Changes in v2: - Update UART7 pins comments. Comments indicated "USART" instead of "UART". -- 2.17.1 diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index fb98a66977fe..21b0906accf3 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1658,6 +1658,36 @@ }; }; + uart7_pins_c: uart7-1 { + pins1 { + pinmux = ; /* UART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART7_RX */ + bias-disable; + }; + }; + + uart7_idle_pins_c: uart7-idle-1 { + pins1 { + pinmux = ; /* UART7_TX */ + }; + pins2 { + pinmux = ; /* UART7_RX */ + bias-disable; + }; + }; + + uart7_sleep_pins_c: uart7-sleep-1 { + pins { + pinmux = , /* UART7_TX */ + ; /* UART7_RX */ + }; + }; + uart8_pins_a: uart8-0 { pins1 { pinmux = ; /* UART8_TX */ @@ -1719,6 +1749,42 @@ }; }; + usart2_pins_c: usart2-0 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_idle_pins_c: usart2-idle-0 { + pins1 { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + ; /* USART2_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_c: usart2-sleep-0 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; + usart3_pins_a: usart3-0 { pins1 { pinmux = ; /* USART3_TX */ @@ -1732,6 +1798,78 @@ }; }; + usart3_pins_b: usart3-0 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART3_RX */ + ; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + + usart3_idle_pins_b: usart3-idle-0 { + pins1 { + pinmux = , /* USART3_TX */ + , /* USART3_RTS */ + ; /* USART3_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART3_RX */ + bias-disable; + }; + }; + + usart3_sleep_pins_b: usart3-sleep-0 { + pins { + pinmux = , /* USART3_TX */ + , /* USART3_RTS */ + , /* USART3_CTS_NSS */ + ; /* USART3_RX */ + }; + }; + + usart3_pins_c: usart3-1 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART3_RX */ + ; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + + usart3_idle_pins_c: usart3-idle-1 { + pins1 { + pinmux = , /* USART3_TX */ + , /* USART3_RTS */ + ; /* USART3_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART3_RX */ + bias-disable; + }; + }; + + usart3_sleep_pins_c: usart3-sleep-1 { + pins { + pinmux = , /* USART3_TX */ + , /* USART3_RTS */ + , /* USART3_CTS_NSS */ + ; /* USART3_RX */ + }; + }; + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = ; /* OTG_ID */