From patchwork Wed Jun 17 03:00:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Hao X-Patchwork-Id: 198971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82282C433DF for ; Wed, 17 Jun 2020 03:01:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 60AA22073E for ; Wed, 17 Jun 2020 03:01:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="uyynP4LV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726780AbgFQDBT (ORCPT ); Tue, 16 Jun 2020 23:01:19 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:33879 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726753AbgFQDBO (ORCPT ); Tue, 16 Jun 2020 23:01:14 -0400 X-UUID: 2199202b9e9d46e7b7348b334e5d656a-20200617 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=tkakusBQyxgP04a3jC23uWYdoIiyLQlQm27PNB6jVwY=; b=uyynP4LVTAjBTen8TtUbTeflr+SNSz6ICzuiPNlrvAqk6uRcMf+9Ns77mB7iWg9dv/U4malFJkzIuiUxU4isrc7dvT3uZEyHJ2XNmLqEMfj2WsdH5sI6H+QOi2BCo0sDDVLKZZl8a6O6D+GFLzZ/E3Or4XvMetfQqTLGhJnRDpM=; X-UUID: 2199202b9e9d46e7b7348b334e5d656a-20200617 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 971613930; Wed, 17 Jun 2020 11:01:08 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 11:01:02 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 17 Jun 2020 11:01:00 +0800 From: Chao Hao To: Joerg Roedel , Rob Herring , Matthias Brugger CC: , , , , , , Yong Wu , FY Yang , Chao Hao Subject: [PATCH v4 4/7] iommu/mediatek: Move inv_sel_reg into the plat_data Date: Wed, 17 Jun 2020 11:00:26 +0800 Message-ID: <20200617030029.4082-5-chao.hao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200617030029.4082-1-chao.hao@mediatek.com> References: <20200617030029.4082-1-chao.hao@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 9A84840B6F993EE5A68EC36BD397D22E6AF46A9C2AC5DC1368FCE26DA913A3182000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For mt6779, MMU_INV_SEL register's offset is changed from 0x38 to 0x2c, so we can put inv_sel_reg in the plat_data to use it. In addition, we renamed it to REG_MMU_INV_SEL_GEN1 and use it before mt6779. Change since v3: 1. Fix coding style Cc: Yong Wu Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 19 +++++++++++-------- drivers/iommu/mtk_iommu.h | 1 + 2 files changed, 12 insertions(+), 8 deletions(-) -- 2.18.0 diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 239d2cdbbc9f..f23919feba4e 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -37,7 +37,7 @@ #define REG_MMU_INVLD_START_A 0x024 #define REG_MMU_INVLD_END_A 0x028 -#define REG_MMU_INV_SEL 0x038 +#define REG_MMU_INV_SEL_GEN1 0x038 #define F_INVLD_EN0 BIT(0) #define F_INVLD_EN1 BIT(1) @@ -168,7 +168,7 @@ static void mtk_iommu_tlb_flush_all(void *cookie) for_each_m4u(data) { writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, - data->base + REG_MMU_INV_SEL); + data->base + data->plat_data->inv_sel_reg); writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); wmb(); /* Make sure the tlb flush all done */ } @@ -185,7 +185,7 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, for_each_m4u(data) { spin_lock_irqsave(&data->tlb_lock, flags); writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, - data->base + REG_MMU_INV_SEL); + data->base + data->plat_data->inv_sel_reg); writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A); writel_relaxed(iova + size - 1, @@ -773,11 +773,12 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = { }; static const struct mtk_iommu_plat_data mt2712_data = { - .m4u_plat = M4U_MT2712, - .has_4gb_mode = true, - .has_bclk = true, - .has_vld_pa_rng = true, - .larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, + .m4u_plat = M4U_MT2712, + .has_4gb_mode = true, + .has_bclk = true, + .has_vld_pa_rng = true, + .inv_sel_reg = REG_MMU_INV_SEL_GEN1, + .larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, }; static const struct mtk_iommu_plat_data mt8173_data = { @@ -785,12 +786,14 @@ static const struct mtk_iommu_plat_data mt8173_data = { .has_4gb_mode = true, .has_bclk = true, .reset_axi = true, + .inv_sel_reg = REG_MMU_INV_SEL_GEN1, .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */ }; static const struct mtk_iommu_plat_data mt8183_data = { .m4u_plat = M4U_MT8183, .reset_axi = true, + .inv_sel_reg = REG_MMU_INV_SEL_GEN1, .larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1}, }; diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index d711ac630037..afd7a2de5c1e 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -43,6 +43,7 @@ struct mtk_iommu_plat_data { bool has_misc_ctrl; bool has_vld_pa_rng; bool reset_axi; + u32 inv_sel_reg; unsigned char larbid_remap[MTK_LARB_NR_MAX]; };