From patchwork Tue May 19 22:41:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lubomir Rintel X-Patchwork-Id: 200328 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A734C433E0 for ; Tue, 19 May 2020 22:42:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 01537205CB for ; Tue, 19 May 2020 22:42:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728380AbgESWmh (ORCPT ); Tue, 19 May 2020 18:42:37 -0400 Received: from v6.sk ([167.172.42.174]:58676 "EHLO v6.sk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728191AbgESWmg (ORCPT ); Tue, 19 May 2020 18:42:36 -0400 Received: from localhost (v6.sk [IPv6:::1]) by v6.sk (Postfix) with ESMTP id 18704610DD; Tue, 19 May 2020 22:42:05 +0000 (UTC) From: Lubomir Rintel To: Stephen Boyd Cc: Michael Turquette , Rob Herring , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Lubomir Rintel Subject: [PATCH v3 06/13] clk: mmp2: Rename mmp2_pll_init() to mmp2_main_clk_init() Date: Wed, 20 May 2020 00:41:44 +0200 Message-Id: <20200519224151.2074597-7-lkundrak@v3.sk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200519224151.2074597-1-lkundrak@v3.sk> References: <20200519224151.2074597-1-lkundrak@v3.sk> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This is a trivial rename for a routine that registers more clock sources than the PLLs -- there's also a XO. Signed-off-by: Lubomir Rintel --- drivers/clk/mmp/clk-of-mmp2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c index 524574187c17..ac88ea99b7c6 100644 --- a/drivers/clk/mmp/clk-of-mmp2.c +++ b/drivers/clk/mmp/clk-of-mmp2.c @@ -139,7 +139,7 @@ static struct mmp_clk_factor_tbl uart_factor_tbl[] = { {.num = 3521, .den = 689}, /*19.23MHZ */ }; -static void mmp2_pll_init(struct mmp2_clk_unit *pxa_unit) +static void mmp2_main_clk_init(struct mmp2_clk_unit *pxa_unit) { struct clk *clk; struct mmp_clk_unit *unit = &pxa_unit->unit; @@ -456,7 +456,7 @@ static void __init mmp2_clk_init(struct device_node *np) mmp_clk_init(np, &pxa_unit->unit, MMP2_NR_CLKS); - mmp2_pll_init(pxa_unit); + mmp2_main_clk_init(pxa_unit); mmp2_apb_periph_clk_init(pxa_unit);