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Thu, 14 May 2020 05:03:15 +0000 From: To: , , CC: , , , , , Subject: [PATCH 12/16] ARM: dts: at91: sama5d2: Add missing flexcom definitions Thread-Topic: [PATCH 12/16] ARM: dts: at91: sama5d2: Add missing flexcom definitions Thread-Index: AQHWKaz5XueFWLPwRk6ZXAr8TP7nXw== Date: Thu, 14 May 2020 05:03:15 +0000 Message-ID: <20200514050301.147442-13-tudor.ambarus@microchip.com> References: <20200514050301.147442-1-tudor.ambarus@microchip.com> In-Reply-To: <20200514050301.147442-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: bootlin.com; dkim=none (message not signed) header.d=none; bootlin.com; dmarc=none action=none header.from=microchip.com; x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 522b823b-c50d-447b-2060-08d7f7c41c2e x-ms-traffictypediagnostic: BY5PR11MB4040: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-bypassexternaltag: True x-ms-oob-tlc-oobclassifiers: OLM:3044; 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DIR:OUT; SFP:1101; x-ms-exchange-antispam-messagedata: Prj3KiDBk7gCdAogjzFFYpIjko2PUeo/f96M/CTMF1+UZ+MmHuRu0RLk1Hrmocan9G6dDqY41ql+Jkc/qSKW78ZMZvjF2ktBzhyEdOD/4XrlrTcTKwYV8cHdfPvaGcWPdzh0ZdODsMm4MP5pvfOGMf56x7GUERsdQhGf8PoZHu4w4TtaG02L7oKW59SjEPab7yVsvDQBCx2qU6f/RjYWHWOWu7dQVURKQOkcpY8WowueD2k+TCO0i2+KNowz5gTLs8sGt/QLEntaqKYQzAj06EVqUkVu9dpw4rgbHCsTlWds9n7BCkJ58vPgogWGqmgUy6HGNu0Ol6Z4IVuk1ke/3f8k7Jkii51tN66K//zrT49axzwetGWKD69BMZ0TJQYt/GNdCtZ29zf17FuakdOQ+GSN73BqM6/JMT4xhNv0ZxnGA29WbHUrSLkfEgY8fotwrSks3eDhEIUIfjnx+y/pq/66woG/XEW1KU87iBxBE0KrBhlDrOzIpr4yKol+9yw6 MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 522b823b-c50d-447b-2060-08d7f7c41c2e X-MS-Exchange-CrossTenant-originalarrivaltime: 14 May 2020 05:03:15.3091 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: PT1bvCVJ5mCMrPdwhszdbdiSt7czoPYMoXe4pzOHAmTJ0PSOVkEnWY8cVPlP0s+oCpfaEeRWoP+Eqi8l1CPZ8btKcXnQ4tzsBmQE4AXJjOU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB4040 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Tudor Ambarus Describe all the flexcom functions for all the flexcom nodes. Signed-off-by: Tudor Ambarus --- arch/arm/boot/dts/sama5d2.dtsi | 79 ++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 5bba8024f485..b8cdeedee6bc 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -723,6 +723,25 @@ status = "disabled"; }; + spi3: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + i2c3: i2c@600 { compatible = "atmel,sama5d2-i2c"; reg = <0x600 0x200>; @@ -910,6 +929,45 @@ atmel,fifo-size = <32>; status = "disabled"; }; + + spi4: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c4: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; flx3: flexcom@fc014000 { @@ -958,6 +1016,27 @@ atmel,fifo-size = <16>; status = "disabled"; }; + + i2c5: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; flx4: flexcom@fc018000 {