From patchwork Sat May 9 08:36:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Hao X-Patchwork-Id: 200849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FA87C47254 for ; Sat, 9 May 2020 08:40:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1C21D2496A for ; Sat, 9 May 2020 08:40:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="MRRXnXiF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728045AbgEIIkY (ORCPT ); Sat, 9 May 2020 04:40:24 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:34224 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728010AbgEIIkY (ORCPT ); Sat, 9 May 2020 04:40:24 -0400 X-UUID: 57a394ace62a4cacbe7dec24340acc29-20200509 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=nxNKFtFcVgXCGJ4BNQwJD0XYyDxH3mH6r9HcI8tiLlE=; b=MRRXnXiFne5u4hG0nWXHIcudRfO+wupWcG7XMPe5fCbaeTSAkdGMWs9CiZQ244FRrkiJtMnbGEQynPH3Mxr6ZApWk4tR5TSGy8lm/vaNP9rCUgSTaetCKMzmH0x+GOxZ5zdZDcg1cbP+le3VkHmthaW6qrW2IWqTi+LPN56Svg4=; X-UUID: 57a394ace62a4cacbe7dec24340acc29-20200509 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1637859311; Sat, 09 May 2020 16:40:19 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 9 May 2020 16:40:17 +0800 Received: from localhost.localdomain (10.15.20.246) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 9 May 2020 16:40:16 +0800 From: Chao Hao To: Joerg Roedel , Rob Herring , Matthias Brugger CC: , , , , , , Chao Hao , Yong Wu , FY Yang , Jun Yan Subject: [PATCH v3 6/7] iommu/mediatek: Add REG_MMU_WR_LEN definition preparing for mt6779 Date: Sat, 9 May 2020 16:36:53 +0800 Message-ID: <20200509083654.5178-7-chao.hao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200509083654.5178-1-chao.hao@mediatek.com> References: <20200509083654.5178-1-chao.hao@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some platforms(ex: mt6779) have a new register called by REG_MMU_WR_LEN to improve performance. This patch add this register definition. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 10 ++++++++++ drivers/iommu/mtk_iommu.h | 2 ++ 2 files changed, 12 insertions(+) -- 2.18.0 diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 3914c418d1b0..dc9ae944e712 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -45,6 +45,8 @@ #define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) #define REG_MMU_DCM_DIS 0x050 +#define REG_MMU_WR_LEN 0x054 +#define F_MMU_WR_THROT_DIS_BIT (BIT(5) | BIT(21)) #define REG_MMU_CTRL_REG 0x110 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) @@ -592,6 +594,12 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); } writel_relaxed(0, data->base + REG_MMU_DCM_DIS); + if (data->plat_data->has_wr_len) { + /* write command throttling mode */ + regval = readl_relaxed(data->base + REG_MMU_WR_LEN); + regval &= ~F_MMU_WR_THROT_DIS_BIT; + writel_relaxed(regval, data->base + REG_MMU_WR_LEN); + } if (data->plat_data->has_misc_ctrl) { regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); @@ -744,6 +752,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev) struct mtk_iommu_suspend_reg *reg = &data->reg; void __iomem *base = data->base; + reg->wr_len = readl_relaxed(base + REG_MMU_WR_LEN); reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); @@ -768,6 +777,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev) dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); return ret; } + writel_relaxed(reg->wr_len, base + REG_MMU_WR_LEN); writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index d51ff99c2c71..9971cedd72ea 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -25,6 +25,7 @@ struct mtk_iommu_suspend_reg { u32 int_main_control; u32 ivrp_paddr; u32 vld_pa_rng; + u32 wr_len; }; enum mtk_iommu_plat { @@ -43,6 +44,7 @@ struct mtk_iommu_plat_data { bool has_misc_ctrl; bool has_sub_comm; bool has_vld_pa_rng; + bool has_wr_len; bool reset_axi; u32 inv_sel_reg; unsigned char larbid_remap[8][4];