From patchwork Sat May 9 08:36:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Hao X-Patchwork-Id: 200850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1AD7C47257 for ; Sat, 9 May 2020 08:40:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 94E422495C for ; Sat, 9 May 2020 08:40:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Xp+IWSS/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728060AbgEIIkZ (ORCPT ); Sat, 9 May 2020 04:40:25 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:49373 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728007AbgEIIkY (ORCPT ); Sat, 9 May 2020 04:40:24 -0400 X-UUID: 3a659193b7cc4238a6993e8efbfb5df3-20200509 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=rPAnzwaR6O/GGAIhKQLkHATI14Jacs04rANBVEp2mY0=; b=Xp+IWSS/nf5d5eLxm/0xWpJMa0TyoXi4zrnBnzhZb4qLZoPnF5UwoUgKsutoWmB6AT6cjg+E636O2uhwVKKfsLo2XPmhdWVLUAxRGiyzSnJ82R3FHKkC68GZY2chsJJRmfLo4q6mFM6oPR7q7XnfO1yAtMLKALlobpEd7GwUe/U=; X-UUID: 3a659193b7cc4238a6993e8efbfb5df3-20200509 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1600407145; Sat, 09 May 2020 16:40:19 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 9 May 2020 16:40:14 +0800 Received: from localhost.localdomain (10.15.20.246) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 9 May 2020 16:40:13 +0800 From: Chao Hao To: Joerg Roedel , Rob Herring , Matthias Brugger CC: , , , , , , Chao Hao , Yong Wu , FY Yang , Jun Yan Subject: [PATCH v3 5/7] iommu/mediatek: Add sub_comm id in translation fault Date: Sat, 9 May 2020 16:36:52 +0800 Message-ID: <20200509083654.5178-6-chao.hao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200509083654.5178-1-chao.hao@mediatek.com> References: <20200509083654.5178-1-chao.hao@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: A3C151D800C9A29925EFA4791AFBA4D946A49C30C4A8135BEDDDE73D30FB8C6F2000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The max larb number that a iommu HW support is 8(larb0~larb7 in the below diagram). If the larb's number is over 8, we use a sub_common for merging several larbs into one larb. At this case, we will extend larb_id: bit[11:9] means common-id; bit[8:7] means subcommon-id; >From these two variable, we could get the real larb number when translation fault happen. The diagram is as below: EMI | IOMMU | ----------------- | | common1 common0 | | ----------------- | smi common | ------------------------------------ | | | | | | 3'd0 3'd1 3'd2 3'd3 ... 3'd7 <-common_id(max is 8) | | | | | | Larb0 Larb1 | Larb3 ... Larb7 | smi sub common | -------------------------- | | | | 2'd0 2'd1 2'd2 2'd3 <-sub_common_id(max is 4) | | | | Larb8 Larb9 Larb10 Larb11 In this patch we extern larb_remap[] to larb_remap[8][4] for this. larb_remap[x][y]: x mean common-id above, y means subcommon_id above. We can also distinguish if the M4U HW has sub_common by has_sub_comm property. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 20 +++++++++++++------- drivers/iommu/mtk_iommu.h | 3 ++- 2 files changed, 15 insertions(+), 8 deletions(-) -- 2.18.0 diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index d73de987f8be..3914c418d1b0 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -90,6 +90,8 @@ #define REG_MMU1_INVLD_PA 0x148 #define REG_MMU0_INT_ID 0x150 #define REG_MMU1_INT_ID 0x154 +#define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7) +#define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) @@ -228,7 +230,7 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) struct mtk_iommu_data *data = dev_id; struct mtk_iommu_domain *dom = data->m4u_dom; u32 int_state, regval, fault_iova, fault_pa; - unsigned int fault_larb, fault_port; + unsigned int fault_larb, fault_port, sub_comm = 0; bool layer, write; /* Read error info from registers */ @@ -244,10 +246,14 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) } layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; - fault_larb = F_MMU_INT_ID_LARB_ID(regval); fault_port = F_MMU_INT_ID_PORT_ID(regval); - - fault_larb = data->plat_data->larbid_remap[fault_larb]; + if (data->plat_data->has_sub_comm) { + fault_larb = F_MMU_INT_ID_COMM_ID(regval); + sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); + } else { + fault_larb = F_MMU_INT_ID_LARB_ID(regval); + } + fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; if (report_iommu_fault(&dom->domain, data->dev, fault_iova, write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { @@ -785,7 +791,7 @@ static const struct mtk_iommu_plat_data mt2712_data = { .has_bclk = true, .has_vld_pa_rng = true, .inv_sel_reg = REG_MMU_INV_SEL_GEN1, - .larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, + .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, }; static const struct mtk_iommu_plat_data mt8173_data = { @@ -794,14 +800,14 @@ static const struct mtk_iommu_plat_data mt8173_data = { .has_bclk = true, .reset_axi = true, .inv_sel_reg = REG_MMU_INV_SEL_GEN1, - .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */ + .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ }; static const struct mtk_iommu_plat_data mt8183_data = { .m4u_plat = M4U_MT8183, .reset_axi = true, .inv_sel_reg = REG_MMU_INV_SEL_GEN1, - .larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1}, + .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, }; static const struct of_device_id mtk_iommu_of_ids[] = { diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index afd7a2de5c1e..d51ff99c2c71 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -41,10 +41,11 @@ struct mtk_iommu_plat_data { /* HW will use the EMI clock if there isn't the "bclk". */ bool has_bclk; bool has_misc_ctrl; + bool has_sub_comm; bool has_vld_pa_rng; bool reset_axi; u32 inv_sel_reg; - unsigned char larbid_remap[MTK_LARB_NR_MAX]; + unsigned char larbid_remap[8][4]; }; struct mtk_iommu_domain;