From patchwork Wed May 6 17:42:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 201006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDEBAC4725E for ; Wed, 6 May 2020 17:45:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B8F8B208DB for ; Wed, 6 May 2020 17:45:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730336AbgEFRo1 (ORCPT ); Wed, 6 May 2020 13:44:27 -0400 Received: from mail.baikalelectronics.com ([87.245.175.226]:32814 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730263AbgEFRoW (ORCPT ); Wed, 6 May 2020 13:44:22 -0400 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 948DE8000B81; Wed, 6 May 2020 17:44:19 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id yB4vVyCw6pxE; Wed, 6 May 2020 20:44:19 +0300 (MSK) From: To: Thomas Bogendoerfer CC: Serge Semin , Serge Semin , Alexey Malahov , Paul Burton , Ralf Baechle , Arnd Bergmann , Rob Herring , , , Allison Randal , Greg Kroah-Hartman , Thomas Gleixner , , Subject: [PATCH v2 14/20] mips: Use offset-sized IO-mem accessors in CPS debug printout Date: Wed, 6 May 2020 20:42:32 +0300 Message-ID: <20200506174238.15385-15-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20200506174238.15385-1-Sergey.Semin@baikalelectronics.ru> References: <20200306124807.3596F80307C2@mail.baikalelectronics.ru> <20200506174238.15385-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Serge Semin Similar to commit 8e5c62e38a88 ("mips: early_printk_8250: Use offset-sized IO-mem accessors") the IO-memory might require to use a proper load/store instructions (like Bailal-T1 IO-memory). To fix the cps-vec UART debug printout lets use the memory access instructions in accordance with the UART registers offset config specified at boot time. Signed-off-by: Serge Semin Cc: Alexey Malahov Cc: Thomas Bogendoerfer Cc: Paul Burton Cc: Ralf Baechle Cc: Arnd Bergmann Cc: Rob Herring Cc: linux-pm@vger.kernel.org Cc: devicetree@vger.kernel.org --- There might be another problem in cps-vec-ns16550.S connected with the difference in CPU/devices endinanness on some platforms. But there is no such for Baikal-T1 SoC. --- arch/mips/kernel/cps-vec-ns16550.S | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/cps-vec-ns16550.S b/arch/mips/kernel/cps-vec-ns16550.S index d5a67b4ce9f6..2adb1c56c7c5 100644 --- a/arch/mips/kernel/cps-vec-ns16550.S +++ b/arch/mips/kernel/cps-vec-ns16550.S @@ -14,16 +14,30 @@ #define UART_TX_OFS (UART_TX << CONFIG_MIPS_CPS_NS16550_SHIFT) #define UART_LSR_OFS (UART_LSR << CONFIG_MIPS_CPS_NS16550_SHIFT) +#if CONFIG_MIPS_CPS_NS16550_SHIFT == 0 +# define UART_L lb +# define UART_S sb +#elif CONFIG_MIPS_CPS_NS16550_SHIFT == 1 +# define UART_L lh +# define UART_S sh +#elif CONFIG_MIPS_CPS_NS16550_SHIFT == 2 +# define UART_L lw +# define UART_S sw +#else +# define UART_L lw +# define UART_S sb +#endif + /** * _mips_cps_putc() - write a character to the UART * @a0: ASCII character to write * @t9: UART base address */ LEAF(_mips_cps_putc) -1: lw t0, UART_LSR_OFS(t9) +1: UART_L t0, UART_LSR_OFS(t9) andi t0, t0, UART_LSR_TEMT beqz t0, 1b - sb a0, UART_TX_OFS(t9) + UART_S a0, UART_TX_OFS(t9) jr ra END(_mips_cps_putc)