From patchwork Tue May 5 16:52:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 201067 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33237C47259 for ; Tue, 5 May 2020 16:52:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1E82C2078C for ; Tue, 5 May 2020 16:52:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730388AbgEEQwp (ORCPT ); Tue, 5 May 2020 12:52:45 -0400 Received: from foss.arm.com ([217.140.110.172]:45500 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730251AbgEEQwp (ORCPT ); Tue, 5 May 2020 12:52:45 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F004B31B; Tue, 5 May 2020 09:52:44 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D6E283F305; Tue, 5 May 2020 09:52:43 -0700 (PDT) From: Andre Przywara To: Rob Herring , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mark Rutland Subject: [PATCH 14/16] arm64: dts: juno: Fix GPU interrupt order Date: Tue, 5 May 2020 17:52:10 +0100 Message-Id: <20200505165212.76466-15-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200505165212.76466-1-andre.przywara@arm.com> References: <20200505165212.76466-1-andre.przywara@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Mali binding insists on the GPU interrupts to be in ordered as: job, mmu, gpu. Sort the GPU interrupts and interrupt-names properties accordingly. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/arm/juno-base.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index a1bdaf455a5c..9a2a8d23fd1e 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -501,10 +501,10 @@ gpu: gpu@2d000000 { compatible = "arm,juno-mali", "arm,mali-t624"; reg = <0 0x2d000000 0 0x10000>; - interrupts = , - , - ; - interrupt-names = "gpu", "job", "mmu"; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; clocks = <&scpi_dvfs 2>; power-domains = <&scpi_devpd 1>; dma-coherent;