From patchwork Thu Apr 30 12:46:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 201302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEF18C8300C for ; Thu, 30 Apr 2020 12:46:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D67F62078D for ; Thu, 30 Apr 2020 12:46:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727061AbgD3MqS convert rfc822-to-8bit (ORCPT ); Thu, 30 Apr 2020 08:46:18 -0400 Received: from skedge03.snt-world.com ([91.208.41.68]:54846 "EHLO skedge03.snt-world.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726520AbgD3MqR (ORCPT ); Thu, 30 Apr 2020 08:46:17 -0400 Received: from sntmail10s.snt-is.com (unknown [10.203.32.183]) by skedge03.snt-world.com (Postfix) with ESMTP id 6647267A902; Thu, 30 Apr 2020 14:46:14 +0200 (CEST) Received: from sntmail12r.snt-is.com (10.203.32.182) by sntmail10s.snt-is.com (10.203.32.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1913.5; Thu, 30 Apr 2020 14:46:14 +0200 Received: from sntmail12r.snt-is.com ([fe80::e551:8750:7bba:3305]) by sntmail12r.snt-is.com ([fe80::e551:8750:7bba:3305%3]) with mapi id 15.01.1913.007; Thu, 30 Apr 2020 14:46:14 +0200 From: Schrempf Frieder To: Adam Ford , Anson Huang , Christian Gmeiner , Daniel Baluta , Fabio Estevam , Schrempf Frieder , Leonard Crestez , "Li Jun" , Lucas Stach , NXP Linux Team , Peng Fan , Pengutronix Kernel Team , Russell King , "Sascha Hauer" , Shawn Guo , "S.j. Wang" CC: "devicetree@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "etnaviv@lists.freedesktop.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: [RFC PATCH 3/4] drm/etnaviv: Change order of enabling clocks to fix boot on i.MX8MM Thread-Topic: [RFC PATCH 3/4] drm/etnaviv: Change order of enabling clocks to fix boot on i.MX8MM Thread-Index: AQHWHu1V9EwL5xxa+UiJnz7nneFudQ== Date: Thu, 30 Apr 2020 12:46:13 +0000 Message-ID: <20200430124602.14463-4-frieder.schrempf@kontron.de> References: <20200430124602.14463-1-frieder.schrempf@kontron.de> In-Reply-To: <20200430124602.14463-1-frieder.schrempf@kontron.de> Accept-Language: de-DE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.17.1 x-originating-ip: [172.25.9.193] x-c2processedorg: 51b406b7-48a2-4d03-b652-521f56ac89f3 MIME-Version: 1.0 X-SnT-MailScanner-Information: Please contact the ISP for more information X-SnT-MailScanner-ID: 6647267A902.ADBD3 X-SnT-MailScanner: Not scanned: please contact your Internet E-Mail Service Provider for details X-SnT-MailScanner-SpamCheck: X-SnT-MailScanner-From: frieder.schrempf@kontron.de X-SnT-MailScanner-To: aford173@gmail.com, anson.huang@nxp.com, christian.gmeiner@gmail.com, daniel.baluta@nxp.com, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, etnaviv@lists.freedesktop.org, festevam@gmail.com, jun.li@nxp.com, kernel@pengutronix.de, l.stach@pengutronix.de, leonard.crestez@nxp.com, linux+etnaviv@armlinux.org.uk, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, peng.fan@nxp.com, s.hauer@pengutronix.de, shawnguo@kernel.org, shengjiu.wang@nxp.com Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Frieder Schrempf On some i.MX8MM devices the boot hangs when enabling the GPU clocks. Changing the order of clock initalization to core -> shader -> bus -> reg fixes the issue. This is the same order used in the imx platform code of the downstream GPU driver in the NXP kernel [1]. For the sake of consistency we also adjust the order of disabling the clocks to the reverse. [1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx.c?h=imx_5.4.3_2.0.0#n1538 Signed-off-by: Frieder Schrempf --- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 42 +++++++++++++-------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index 7b138d4dd068..424b2e5951f0 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -1487,55 +1487,55 @@ static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) { int ret; - if (gpu->clk_reg) { - ret = clk_prepare_enable(gpu->clk_reg); + if (gpu->clk_core) { + ret = clk_prepare_enable(gpu->clk_core); if (ret) return ret; } - if (gpu->clk_bus) { - ret = clk_prepare_enable(gpu->clk_bus); + if (gpu->clk_shader) { + ret = clk_prepare_enable(gpu->clk_shader); if (ret) - goto disable_clk_reg; + goto disable_clk_core; } - if (gpu->clk_core) { - ret = clk_prepare_enable(gpu->clk_core); + if (gpu->clk_bus) { + ret = clk_prepare_enable(gpu->clk_bus); if (ret) - goto disable_clk_bus; + goto disable_clk_shader; } - if (gpu->clk_shader) { - ret = clk_prepare_enable(gpu->clk_shader); + if (gpu->clk_reg) { + ret = clk_prepare_enable(gpu->clk_reg); if (ret) - goto disable_clk_core; + goto disable_clk_bus; } return 0; -disable_clk_core: - if (gpu->clk_core) - clk_disable_unprepare(gpu->clk_core); disable_clk_bus: if (gpu->clk_bus) clk_disable_unprepare(gpu->clk_bus); -disable_clk_reg: - if (gpu->clk_reg) - clk_disable_unprepare(gpu->clk_reg); +disable_clk_shader: + if (gpu->clk_shader) + clk_disable_unprepare(gpu->clk_shader); +disable_clk_core: + if (gpu->clk_core) + clk_disable_unprepare(gpu->clk_core); return ret; } static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) { + if (gpu->clk_reg) + clk_disable_unprepare(gpu->clk_reg); + if (gpu->clk_bus) + clk_disable_unprepare(gpu->clk_bus); if (gpu->clk_shader) clk_disable_unprepare(gpu->clk_shader); if (gpu->clk_core) clk_disable_unprepare(gpu->clk_core); - if (gpu->clk_bus) - clk_disable_unprepare(gpu->clk_bus); - if (gpu->clk_reg) - clk_disable_unprepare(gpu->clk_reg); return 0; }