From patchwork Mon Apr 20 12:16:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 201762 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A37A6C3815B for ; Mon, 20 Apr 2020 12:16:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 839DB206F6 for ; Mon, 20 Apr 2020 12:16:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=st.com header.i=@st.com header.b="fh9p1vMp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726880AbgDTMQp (ORCPT ); Mon, 20 Apr 2020 08:16:45 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:61584 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725944AbgDTMQo (ORCPT ); Mon, 20 Apr 2020 08:16:44 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03KBrrCn025529; Mon, 20 Apr 2020 14:16:33 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=1o0Izbp2L810/aRMfi0HxXPaokBREpCphH53oslSJGg=; b=fh9p1vMpZkJl7kpC2g1SwvICm/SQctpEoQ3/h9VAiSdaWMQgB856E3fVUX2en25pCyRR BviFh/2DKiDivYTMcqKuVFPW4BoMJXLo0ln3T8Z25G1EIfnKl1FSPe00z2RgTRz7+P7J C2TnfcFmZBLuIZvRgx0bR3M3se4LqdU6JbNYoUsqG7OEjChWEH/WIm1PwUTqweNkvwfw a1UPWSE+ke6vizne903/d2tpnMhMqZkfOSmnFe6qf8blwoYWPtziRMueTEEYsZvLGzuf NlwSr3JhLFXOjTxAg4pKQdrJfPIkzeD1X4ZXj8fF5t5IO+KxIZqYV+FYg/qdc1SN+Ugw hg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 30fq11a66x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 20 Apr 2020 14:16:33 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2408110002A; Mon, 20 Apr 2020 14:16:33 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag3node3.st.com [10.75.127.9]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 4C71820FA78; Mon, 20 Apr 2020 14:16:32 +0200 (CEST) Received: from localhost (10.75.127.51) by SFHDAG3NODE3.st.com (10.75.127.9) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 20 Apr 2020 14:16:31 +0200 From: Benjamin Gaignard To: , , , , , , , CC: , , , , Benjamin Gaignard Subject: [PATCH v7 3/6] mfd: stm32: Add defines to be used for clkevent purpose Date: Mon, 20 Apr 2020 14:16:17 +0200 Message-ID: <20200420121620.2099-4-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20200420121620.2099-1-benjamin.gaignard@st.com> References: <20200420121620.2099-1-benjamin.gaignard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.51] X-ClientProxiedBy: SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG3NODE3.st.com (10.75.127.9) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-20_03:2020-04-20,2020-04-20 signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add defines to be able to enable/clear irq and configure one shot mode. Signed-off-by: Benjamin Gaignard Acked-by: Lee Jones --- include/linux/mfd/stm32-lptimer.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/linux/mfd/stm32-lptimer.h b/include/linux/mfd/stm32-lptimer.h index 605f62264825..90b20550c1c8 100644 --- a/include/linux/mfd/stm32-lptimer.h +++ b/include/linux/mfd/stm32-lptimer.h @@ -27,10 +27,15 @@ #define STM32_LPTIM_CMPOK BIT(3) /* STM32_LPTIM_ICR - bit fields */ +#define STM32_LPTIM_ARRMCF BIT(1) #define STM32_LPTIM_CMPOKCF_ARROKCF GENMASK(4, 3) +/* STM32_LPTIM_IER - bit flieds */ +#define STM32_LPTIM_ARRMIE BIT(1) + /* STM32_LPTIM_CR - bit fields */ #define STM32_LPTIM_CNTSTRT BIT(2) +#define STM32_LPTIM_SNGSTRT BIT(1) #define STM32_LPTIM_ENABLE BIT(0) /* STM32_LPTIM_CFGR - bit fields */