From patchwork Mon Apr 6 16:04:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 202349 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.3 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 251A3C2BA17 for ; Mon, 6 Apr 2020 16:04:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F114D2222D for ; Mon, 6 Apr 2020 16:04:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1586189073; bh=JCCRj+vTlJ1LFyWa+rT0OROC+0/HKpKiFVbCrYYqdOM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=nPEosirdgxVHwz9wWQk9+IeIJJD8DAhddTtNzvTt0CWcEDzQXOrXlzeMpyStFdQH5 mPFdLaiAqLZSB8g8ivMfWPvuK8xH/aOeuE9+sw0ggzjyvZy//N/hI5ZeTTbsCVGl9M IlwD1nzwHnetvbwCKF7Bc6zPqy8oob8pNAbpVDLY= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729214AbgDFQEc (ORCPT ); Mon, 6 Apr 2020 12:04:32 -0400 Received: from mail.kernel.org ([198.145.29.99]:36172 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728983AbgDFQEc (ORCPT ); Mon, 6 Apr 2020 12:04:32 -0400 Received: from localhost.localdomain (cpe-70-114-128-244.austin.res.rr.com [70.114.128.244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7C10D21D94; Mon, 6 Apr 2020 16:04:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1586189071; bh=JCCRj+vTlJ1LFyWa+rT0OROC+0/HKpKiFVbCrYYqdOM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=d++QJHEIoKstE88mhR+p+cY0L2sSbBJgHFcDUeFF9z91vKIJ4DS2riNmcqsLiekgV Lrnv8gj2IyusKIARrwmjirnhcfnxhShg2GfXWA1jGCmEYsdwGbhgNjJV5GetisbvLa SDr5mGPiVl3iYo3opNc49hRLi/NA32CiNog19KLE= From: Dinh Nguyen To: linux-clk@vger.kernel.org Cc: dinguyen@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com Subject: [PATCHv6 2/5] clk: socfpga: remove clk_ops enable/disable methods Date: Mon, 6 Apr 2020 11:04:15 -0500 Message-Id: <20200406160418.27476-3-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200406160418.27476-1-dinguyen@kernel.org> References: <20200406160418.27476-1-dinguyen@kernel.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The enable/disable clock ops are already defined in the standard clock ops, so we don't need to assign them. Signed-off-by: Dinh Nguyen --- v6: no changes v5: no changes v4: no changes v3: no changes v2: created --- drivers/clk/socfpga/clk-pll-a10.c | 2 -- drivers/clk/socfpga/clk-pll-s10.c | 2 -- drivers/clk/socfpga/clk-pll.c | 2 -- 3 files changed, 6 deletions(-) diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c index 3816fc04b274..6d9395106c0c 100644 --- a/drivers/clk/socfpga/clk-pll-a10.c +++ b/drivers/clk/socfpga/clk-pll-a10.c @@ -102,8 +102,6 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node, pll_clk->hw.hw.init = &init; pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; - clk_pll_ops.enable = clk_gate_ops.enable; - clk_pll_ops.disable = clk_gate_ops.disable; clk = clk_register(NULL, &pll_clk->hw.hw); if (WARN_ON(IS_ERR(clk))) { diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c index bcd3f14e9145..9faa80ff3b53 100644 --- a/drivers/clk/socfpga/clk-pll-s10.c +++ b/drivers/clk/socfpga/clk-pll-s10.c @@ -138,8 +138,6 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks, pll_clk->hw.hw.init = &init; pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER; - clk_pll_ops.enable = clk_gate_ops.enable; - clk_pll_ops.disable = clk_gate_ops.disable; clk = clk_register(NULL, &pll_clk->hw.hw); if (WARN_ON(IS_ERR(clk))) { diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c index dc65cc0fd3bd..a001641b2f42 100644 --- a/drivers/clk/socfpga/clk-pll.c +++ b/drivers/clk/socfpga/clk-pll.c @@ -105,8 +105,6 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node, pll_clk->hw.hw.init = &init; pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; - clk_pll_ops.enable = clk_gate_ops.enable; - clk_pll_ops.disable = clk_gate_ops.disable; clk = clk_register(NULL, &pll_clk->hw.hw); if (WARN_ON(IS_ERR(clk))) {