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[91.167.199.67]) by smtp.gmail.com with ESMTPSA id u13sm21606411wru.88.2020.04.05.03.49.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Apr 2020 03:49:19 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Maxime Ripard , Chen-Yu Tsai , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi , Ondrej Jirman , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH 4/7] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table Date: Sun, 5 Apr 2020 12:49:10 +0200 Message-Id: <20200405104913.22806-5-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200405104913.22806-1-peron.clem@gmail.com> References: <20200405104913.22806-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Ondrej Jirman Add an Operating Performance Points table for the CPU cores to enable Dynamic Voltage & Frequency Scaling on the H6. Signed-off-by: Ondrej Jirman Signed-off-by: Clément Péron --- .../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 103 ++++++++++++++++++ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 + 2 files changed, 107 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi new file mode 100644 index 000000000000..b480c33f426b --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2020 Ondrej Jirman +// Copyright (C) 2020 Clément Péron + +/ { + cpu0_opp_table: opp_table0 { + compatible = "allwinner,sun50i-h6-operating-points"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + opp@480000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <480000000>; + + opp-microvolt-speed0 = <880000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <820000>; + }; + + opp@720000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <720000000>; + + opp-microvolt-speed0 = <880000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <820000>; + }; + + opp@816000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <816000000>; + + opp-microvolt-speed0 = <880000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <820000>; + }; + + opp@888000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <888000000>; + + opp-microvolt-speed0 = <880000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <820000>; + }; + + opp@1080000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1080000000>; + + opp-microvolt-speed0 = <940000>; + opp-microvolt-speed1 = <880000>; + opp-microvolt-speed2 = <880000>; + }; + + opp@1320000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1320000000>; + + opp-microvolt-speed0 = <1000000>; + opp-microvolt-speed1 = <940000>; + opp-microvolt-speed2 = <940000>; + }; + + opp@1488000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1488000000>; + + opp-microvolt-speed0 = <1060000>; + opp-microvolt-speed1 = <1000000>; + opp-microvolt-speed2 = <1000000>; + }; + + opp@1800000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1800000000>; + + opp-microvolt-speed0 = <1160000>; + opp-microvolt-speed1 = <1100000>; + opp-microvolt-speed2 = <1100000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; +}; + +&cpu1 { + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; +}; + +&cpu2 { + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; +}; + +&cpu3 { + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index c3e4f09f60ce..a9304fec245c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -253,6 +253,10 @@ #address-cells = <1>; #size-cells = <1>; + speedbin_efuse: speed@1c { + reg = <0x1c 0x4>; + }; + ths_calibration: thermal-sensor-calibration@14 { reg = <0x14 0x8>; };