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[217.229.22.169]) by smtp.gmail.com with ESMTPSA id o3sm4778931wme.36.2020.03.10.08.20.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2020 08:20:25 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Dmitry Osipenko , Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd , Joseph Lo , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 7/8] arm64: tegra: Add external memory controller node for Tegra210 Date: Tue, 10 Mar 2020 16:20:02 +0100 Message-Id: <20200310152003.2945170-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200310152003.2945170-1-thierry.reding@gmail.com> References: <20200310152003.2945170-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Joseph Lo Add external memory controller (EMC) node for Tegra210 Signed-off-by: Joseph Lo Signed-off-by: Thierry Reding --- Changes in v5: - drop list of clocks because we need very strict ordering that DT can't guarantee - drop hard-coded EMC table, bootloaders should add it dynamically arch/arm64/boot/dts/nvidia/tegra210.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 64c46ce3849d..3fa92dd8350b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -895,6 +895,17 @@ mc: memory-controller@70019000 { #iommu-cells = <1>; }; + external-memory-controller@7001b000 { + compatible = "nvidia,tegra210-emc"; + reg = <0x0 0x7001b000 0x0 0x1000>, + <0x0 0x7001e000 0x0 0x1000>, + <0x0 0x7001f000 0x0 0x1000>; + clocks = <&tegra_car TEGRA210_CLK_EMC>; + clock-names = "emc"; + interrupts = ; + nvidia,memory-controller = <&mc>; + }; + sata@70020000 { compatible = "nvidia,tegra210-ahci"; reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */