From patchwork Sat Feb 22 12:03:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 204427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FA67C35666 for ; Sat, 22 Feb 2020 12:04:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1682E21D56 for ; Sat, 22 Feb 2020 12:04:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="d2T3fGJC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727463AbgBVMEU (ORCPT ); Sat, 22 Feb 2020 07:04:20 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:35042 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727448AbgBVMET (ORCPT ); Sat, 22 Feb 2020 07:04:19 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 01MC4HS4045430; Sat, 22 Feb 2020 06:04:17 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1582373057; bh=hwpuQur3T4AWJCPfzCui/Pmi92qAyFIUmGQ8f+67Yg8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=d2T3fGJCFtVQroQTqmfjQcmNOvArmVU4WBafICX1ChBQdOZPryAFdU+/ZZKtpNsG+ 0etr/I03VDKEqyhBNSjaAWJDVuk8Dp3dYMUtaxD7FyDRDa8LukreGoljMLnql4nXp8 6GNBXIez6o99nHbU/YyPAGuDi7FUgmibgeV2mqkw= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 01MC4Htw001035 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 22 Feb 2020 06:04:17 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Sat, 22 Feb 2020 06:04:16 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Sat, 22 Feb 2020 06:04:16 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 01MC4Gsv018877; Sat, 22 Feb 2020 06:04:16 -0600 From: Grygorii Strashko To: Kishon Vijay Abraham I , Tero Kristo , "David S. Miller" CC: , Sekhar Nori , , , Rob Herring , Grygorii Strashko Subject: [for-next PATCH 4/5] arm64: dts: ti: k3-am65-mcu: add phy-gmii-sel node Date: Sat, 22 Feb 2020 14:03:57 +0200 Message-ID: <20200222120358.10003-5-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200222120358.10003-1-grygorii.strashko@ti.com> References: <20200222120358.10003-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT node for the TI AM65x SoC phy-gmii-sel PHY required for Ethernet ports mode selection. Signed-off-by: Grygorii Strashko --- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 92629cbdc184..8309f49713b4 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -12,6 +12,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x40f00000 0x20000>; + + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4040 0x4>; + #phy-cells = <1>; + }; }; mcu_uart0: serial@40a00000 {