From patchwork Fri Feb 21 13:28:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 204468 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.3 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 326B6C35647 for ; Fri, 21 Feb 2020 13:29:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 08A4724670 for ; Fri, 21 Feb 2020 13:29:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="D4a+fs+x" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728286AbgBUN3e (ORCPT ); Fri, 21 Feb 2020 08:29:34 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:36842 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728255AbgBUN3e (ORCPT ); Fri, 21 Feb 2020 08:29:34 -0500 Received: by mail-wr1-f65.google.com with SMTP id z3so2085071wru.3; Fri, 21 Feb 2020 05:29:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=dL6DkN/eyJeAcyORY4ediiEbEPh4coH4SMwDInRe1/k=; b=D4a+fs+xcSBTPsk7mZHHMfHPe6C5Ij7tTO9DuQP2Gqc0GTyBxxzjn1FvtSPA1qvhOo 2xaCmAXlWRvEYo/dBURhzRcE855YJBgmZ+7Y9gdUC7xTsY/C8HfDKAfqB56Ed5LslGDu kAiWrL1jY/uTvjrIJv8R/q+gxSSE5+xgq2yHJUrXXKt9n6RDf3JpsHl/C50iX+7TerZS rsPyi2Ef/d97qTZ5kT9QHU3lJwrKOYVkNjPdoB9kD0wofbwf/vsdd0t4gBkuZC9zdGpD XDbZES0JWol/TyzHS4WTQ6M44ZEXDzhsJ+xoyScTNHDSBTHvnZT0u3Ccjks9dwg8p4Xf 0ARQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=dL6DkN/eyJeAcyORY4ediiEbEPh4coH4SMwDInRe1/k=; b=iaHErlHQtbx5ljBc0zhLwj3o8dJHBvrgoDNW1LQN10s3Xfeso/QBgYgNgEsccfOWeT OoaYeaDEXzbIFYAjngKedDnsA4YIpnZ+KmwM4E4oXxNsK6iOnwr/FhaLQCckK2OSFtZ8 usvBo3229A1USJl6x1EJ7gnFP28K56nMRWLbLwFZDYFWaqvSPqavTz+ByqZTDQ3ypIMg kyz4mBDl8RBfC4q5KMFdStbsLLCJP6+oa70SwhYrCBIaVDP7YyevgM9kRcCPF6LtsssT RM+hKlSinT8As9htbuVoDFGdiCfWX9w+vmIRAHDI39im8VT5W1ILulMKyKCJLLA2DNhT nRFQ== X-Gm-Message-State: APjAAAWvDZLEhT9JrITTsdrHIGUTwNlqYH38lxiQ6AcuJ2++QEL5gVtQ k8YeQbhDSEiYPiV4NJUuY1U= X-Google-Smtp-Source: APXvYqyt0UiPpZZB/VmC8uuK7JIRQSBPQjnH8YikrAsf6JDVlqKkNimiGgfkNwdzOH/rZOXIGxkEoA== X-Received: by 2002:adf:df0e:: with SMTP id y14mr46895517wrl.377.1582291770378; Fri, 21 Feb 2020 05:29:30 -0800 (PST) Received: from Ansuel-XPS.localdomain (93-39-149-95.ip76.fastwebnet.it. [93.39.149.95]) by smtp.googlemail.com with ESMTPSA id h5sm4172178wmf.8.2020.02.21.05.29.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:29:29 -0800 (PST) From: Ansuel Smith Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , "David S. Miller" , Rob Herring , Mark Rutland , Andrew Lunn , Florian Fainelli , Heiner Kallweit , Russell King , linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/2] net: mdio: add ipq8064 mdio driver Date: Fri, 21 Feb 2020 14:28:31 +0100 Message-Id: <20200221132834.20719-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.0 MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Currently ipq806x soc use generi bitbang driver to comunicate with the gmac ethernet interface. Add a dedicated driver created by chunkeey to fix this. Christian Lamparter Signed-off-by: Ansuel Smith --- drivers/net/phy/Kconfig | 8 ++ drivers/net/phy/Makefile | 1 + drivers/net/phy/mdio-ipq8064.c | 166 +++++++++++++++++++++++++++++++++ 3 files changed, 175 insertions(+) create mode 100644 drivers/net/phy/mdio-ipq8064.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 9dabe03a668c..ec2a5493a7e8 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -157,6 +157,14 @@ config MDIO_I2C This is library mode. +config MDIO_IPQ8064 + tristate "Qualcomm IPQ8064 MDIO interface support" + depends on HAS_IOMEM && OF_MDIO + depends on MFD_SYSCON + help + This driver supports the MDIO interface found in the network + interface units of the IPQ8064 SoC + config MDIO_MOXART tristate "MOXA ART MDIO interface support" depends on ARCH_MOXART || COMPILE_TEST diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index fe5badf13b65..8f02bd2089f3 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium.o obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o +obj-$(CONFIG_MDIO_IPQ8064) += mdio-ipq8064.o obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o diff --git a/drivers/net/phy/mdio-ipq8064.c b/drivers/net/phy/mdio-ipq8064.c new file mode 100644 index 000000000000..fd856b798194 --- /dev/null +++ b/drivers/net/phy/mdio-ipq8064.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Qualcomm IPQ8064 MDIO interface driver +// +// Copyright (C) 2019 Christian Lamparter + +#include +#include +#include +#include +#include +#include +#include +#include + +/* MII address register definitions */ +#define MII_ADDR_REG_ADDR 0x10 +#define MII_BUSY BIT(0) +#define MII_WRITE BIT(1) +#define MII_CLKRANGE_60_100M (0 << 2) +#define MII_CLKRANGE_100_150M (1 << 2) +#define MII_CLKRANGE_20_35M (2 << 2) +#define MII_CLKRANGE_35_60M (3 << 2) +#define MII_CLKRANGE_150_250M (4 << 2) +#define MII_CLKRANGE_250_300M (5 << 2) +#define MII_CLKRANGE_MASK GENMASK(4, 2) +#define MII_REG_SHIFT 6 +#define MII_REG_MASK GENMASK(10, 6) +#define MII_ADDR_SHIFT 11 +#define MII_ADDR_MASK GENMASK(15, 11) + +#define MII_DATA_REG_ADDR 0x14 + +#define MII_MDIO_DELAY (1000) +#define MII_MDIO_RETRY (10) + +struct ipq8064_mdio { + struct regmap *base; /* NSS_GMAC0_BASE */ +}; + +static int +ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv) +{ + u32 busy; + + return regmap_read_poll_timeout(priv->base, MII_ADDR_REG_ADDR, busy, + !(busy & MII_BUSY), MII_MDIO_DELAY, + MII_MDIO_RETRY * USEC_PER_MSEC); +} + +static int +ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset) +{ + struct ipq8064_mdio *priv = bus->priv; + u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M; + u32 ret_val; + int err; + + /* Reject clause 45 */ + if (reg_offset & MII_ADDR_C45) + return -EOPNOTSUPP; + + miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) | + ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); + + regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); + usleep_range(10, 20); + + err = ipq8064_mdio_wait_busy(priv); + if (err) + return err; + + regmap_read(priv->base, MII_DATA_REG_ADDR, &ret_val); + return (int)ret_val; +} + +static int +ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data) +{ + struct ipq8064_mdio *priv = bus->priv; + u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M; + + /* Reject clause 45 */ + if (reg_offset & MII_ADDR_C45) + return -EOPNOTSUPP; + + regmap_write(priv->base, MII_DATA_REG_ADDR, data); + + miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) | + ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); + + regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); + usleep_range(10, 20); + + return ipq8064_mdio_wait_busy(priv); +} + +static int +ipq8064_mdio_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct ipq8064_mdio *priv; + struct mii_bus *bus; + int ret; + + bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv)); + if (!bus) + return -ENOMEM; + + bus->name = "ipq8064_mdio_bus"; + bus->read = ipq8064_mdio_read; + bus->write = ipq8064_mdio_write; + snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev)); + bus->parent = &pdev->dev; + + priv = bus->priv; + priv->base = syscon_node_to_regmap(np); + if (IS_ERR(priv->base) && priv->base != ERR_PTR(-EPROBE_DEFER)) + priv->base = syscon_regmap_lookup_by_phandle(np, "master"); + + if (priv->base == ERR_PTR(-EPROBE_DEFER)) { + return -EPROBE_DEFER; + } else if (IS_ERR(priv->base)) { + dev_err(&pdev->dev, "error getting syscon regmap, error=%ld\n", + PTR_ERR(priv->base)); + return PTR_ERR(priv->base); + } + + ret = of_mdiobus_register(bus, np); + if (ret) + return ret; + + platform_set_drvdata(pdev, bus); + return 0; +} + +static int +ipq8064_mdio_remove(struct platform_device *pdev) +{ + struct mii_bus *bus = platform_get_drvdata(pdev); + + mdiobus_unregister(bus); + + return 0; +} + +static const struct of_device_id ipq8064_mdio_dt_ids[] = { + { .compatible = "qcom,ipq8064-mdio" }, + { } +}; +MODULE_DEVICE_TABLE(of, ipq8064_mdio_dt_ids); + +static struct platform_driver ipq8064_mdio_driver = { + .probe = ipq8064_mdio_probe, + .remove = ipq8064_mdio_remove, + .driver = { + .name = "ipq8064-mdio", + .of_match_table = ipq8064_mdio_dt_ids, + }, +}; + +module_platform_driver(ipq8064_mdio_driver); + +MODULE_DESCRIPTION("Qualcomm IPQ8064 MDIO interface driver"); +MODULE_AUTHOR("Christian Lamparter "); +MODULE_LICENSE("GPL");