From patchwork Fri Feb 21 11:28:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 204477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D54DC35653 for ; Fri, 21 Feb 2020 11:29:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E97F9208C4 for ; Fri, 21 Feb 2020 11:29:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="ovexBTzC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727830AbgBUL2u (ORCPT ); Fri, 21 Feb 2020 06:28:50 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:44963 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727827AbgBUL2t (ORCPT ); Fri, 21 Feb 2020 06:28:49 -0500 X-UUID: a8dc2fe4bf9842d09d12808d4b6a7848-20200221 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=zFZhXk7fCqXKk9Mb/Rx6jZKFuJRDTSRGsr1lm/b+5DU=; b=ovexBTzC48RueZbJWZ+GrTK/Hn7xV7SIeRvMI8QvWXNouMt+mRI45xOOZMYQ56YgnItVtHVPx1zQqPqEX1FFtOoCoPOg33SJiApGb4RuZWKPH2JfBYn4NurRWrdJ9285hC2nn+3Utvb/YNqgZ/b69tpbPMRtvVBZTv8zN/Ik6Go=; X-UUID: a8dc2fe4bf9842d09d12808d4b6a7848-20200221 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1467076355; Fri, 21 Feb 2020 19:28:39 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33DR.mediatek.inc (172.27.6.106) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 21 Feb 2020 19:23:59 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 21 Feb 2020 19:27:34 +0800 From: Jitao Shi To: Rob Herring , Mark Rutland , Matthias Brugger , Daniel Vetter , David Airlie , , CC: , , , , , , , , , , , Jitao Shi Subject: [PATCH v6 1/4] dt-bindings: display: mediatek: update dpi supported chips Date: Fri, 21 Feb 2020 19:28:25 +0800 Message-ID: <20200221112828.55837-2-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200221112828.55837-1-jitao.shi@mediatek.com> References: <20200221112828.55837-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 45350EF9107AC20D662E832B95D598681BBB945A8E95C707967860581846053F2000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add decriptions about supported chips, including MT2701 & MT8173 & mt8183 1. Add more chips support. ex. MT2701 & MT8173 & MT8183 2. Add property "dpi_pin_mode_swap" and "pinctrl-names" gpio mode dpi mode and gpio oupput-low to avoid leakage current. 3. Add property "dpi_dual_edge" to config the dpi pin output mode dual edge or single edge sample data. Signed-off-by: Jitao Shi --- .../bindings/display/mediatek/mediatek,dpi.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.21.0 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt index b6a7e7397b8b..cd6a1469c8b7 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt @@ -7,6 +7,7 @@ output bus. Required properties: - compatible: "mediatek,-dpi" + the supported chips are mt2701 , mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - interrupts: The interrupt signal from the function block. - clocks: device clocks @@ -16,6 +17,11 @@ Required properties: Documentation/devicetree/bindings/graph.txt. This port should be connected to the input port of an attached HDMI or LVDS encoder chip. +Optional properties: +- dpi_pin_mode_swap: Swap the pin mode between dpi mode and gpio mode. +- pinctrl-names: Contain "gpiomode" and "dpimode". +- dpi_dual_edge: Control the RGB 24bit data on 12 pins or 24 pins. + Example: dpi0: dpi@1401d000 { @@ -26,6 +32,11 @@ dpi0: dpi@1401d000 { <&mmsys CLK_MM_DPI_ENGINE>, <&apmixedsys CLK_APMIXED_TVDPLL>; clock-names = "pixel", "engine", "pll"; + dpi_dual_edge; + dpi_pin_mode_swap; + pinctrl-names = "gpiomode", "dpimode"; + pinctrl-0 = <&dpi_pin_gpio>; + pinctrl-1 = <&dpi_pin_func>; port { dpi0_out: endpoint {