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Fri, 31 Jan 2020 00:41:56 -0800 (PST) Received: from 1aq-andre.garage.tyco.com ([77.107.218.170]) by smtp.gmail.com with ESMTPSA id x7sm11034302wrq.41.2020.01.31.00.41.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jan 2020 00:41:55 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= To: linux-kernel@vger.kernel.org Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , Ilya Ledvich , Igor Grinberg , Rob Herring , Mark Rutland , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 07/12] ARM: dts: imx7d: cl-som-imx7: add/enable SPI flash on spi1 Date: Fri, 31 Jan 2020 08:36:33 +0000 Message-Id: <20200131083638.6118-7-git@andred.net> X-Mailer: git-send-email 2.23.0.rc1 In-Reply-To: <20200131083638.6118-1-git@andred.net> References: <20200131083638.6118-1-git@andred.net> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org add/enable SPI flash on spi1 using the default vendor's partition layout as per downstream kernel Signed-off-by: André Draszik Cc: Ilya Ledvich Cc: Igor Grinberg Cc: Rob Herring Cc: Mark Rutland Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org --- arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 45 +++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts index ca3c5d95d6c3..d4637a8ca223 100644 --- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts +++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts @@ -28,6 +28,36 @@ cpu-supply = <&sw1a_reg>; }; +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + + partition@0 { + label = "uboot"; + reg = <0x0 0xc0000>; + }; + + partition@c0000 { + label = "uboot environment"; + reg = <0xc0000 0x40000>; + }; + + partition@100000 { + label = "splash"; + reg = <0x100000 0x100000>; + }; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1phy>; @@ -214,6 +244,21 @@ }; &iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0xf + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0xf + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0xf + >; + }; + + pinctrl_ecspi1_cs: ecspi1_cs_grp { + fsl,pins = < + /* SPI flash chipselect */ + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x34 + >; + }; + pinctrl_enet1: enet1grp { fsl,pins = < MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x30