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Thu, 30 Jan 2020 15:36:26 +0000 From: =?iso-8859-2?q?Wojciech_=AFmuda?= To: "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "coresight@lists.linaro.org" CC: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "michal.simek@xilinx.com" , "m.tretter@pengutronix.de" , "nava.manne@xilinx.com" , "antoine.tenart@bootlin.com" , "t-kristo@ti.com" , "rajan.vaja@xilinx.com" , "mathieu.poirier@linaro.org" , Krzysztof Pilch , Michal Mosdorf , =?iso-8859-2?q?Micha=B3_Kurowski?= , =?iso-8859-2?q?Wojciech_=AFmuda?= Subject: [PATCH 1/1] arm64: zynqmp: Add CoreSight components Thread-Topic: [PATCH 1/1] arm64: zynqmp: Add CoreSight components Thread-Index: AQHV14MJZb3vn0JX0kKRRyn8jGwhwg== Date: Thu, 30 Jan 2020 15:36:27 +0000 Message-ID: <20200130153613.20365-2-wzmuda@n7space.com> References: <20200130153613.20365-1-wzmuda@n7space.com> In-Reply-To: <20200130153613.20365-1-wzmuda@n7space.com> Accept-Language: en-US, pl-PL Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM0PR0402CA0031.eurprd04.prod.outlook.com (2603:10a6:208:15::44) To AM0PR03MB3651.eurprd03.prod.outlook.com (2603:10a6:208:42::32) authentication-results: spf=none (sender IP is ) smtp.mailfrom=wzmuda@n7space.com; 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x-microsoft-antispam-message-info: kaRguywCKJtvqFiv6aYNfes0LNKEdCr5c+IpjIiS7p2I0MG8TzDMlCDR/ZMLcPTtd2+1CLMccijmbQg3eltSmvS1JD/WQF6rZnQ/AGhWP6Qo01IYOeyUlE3XI1HH6QWdce1egCE1yJn6W1z9Ym3YsfYaMmYH8fekHRv9kuIJFtp0AwPId5O0cQ029G70YHz2gAJVPOktuR+54r1zryH1CW2IEzEZR6SyXTWJgqMJelHkTZH3IWABqFe0hEkRPFk4oJ1T2E75YTGSth/7dECrpcFNtbL51D3EPW13b88HbCmiJ/uWLy6rCxLuW8KJRPcepllJlmiV36LOJN6bbFKPstGmhNchqHxt9jLHM4C5wgfloSPY16yT0XWYzCu7tcs6xhcyP61GBJk8aD5KATEPf+SizBeJ4+iBIpYmEjzuX+uPCGlNTRg7mN1Jloe4de3c x-ms-exchange-antispam-messagedata: +UHIRO6krTjF798KN0t5akhQNvQoiiKtWuU18NRzp8Han2FSYXmI2WUXPzKlwOykFoyIhC4XN0/1IPoHC38cjPj3uopgcEpRERA77mEBf9FvLBOH7wGjoegBEybMMyWBQwlK5FBQtEJ8Qk1iLlojyA== MIME-Version: 1.0 X-OriginatorOrg: n7space.com X-MS-Exchange-CrossTenant-Network-Message-Id: e582a2f8-fbb1-4f66-b025-08d7a59a2b84 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Jan 2020 15:36:27.1446 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 5938c8fc-39b0-401e-a174-4e3ffe97d69d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: oboDXoRioocURD1BZUw9oA/Tj21L8lmhMkFKuUdXP5NPbXxlfeuoMvr48LOLlDcvQ9PJAIpdXsBnXG0ShVVHdQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR03MB4610 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Wojciech Zmuda Add nodes for the following CoreSight components: - ETMs for A53 cores - debug components for A53 cores - funnel gathering outputs from A53 ETMs and SoC-wide funnels - the only replicator - all TMCs: 4k ETF, 8k ETF and ETR - TPIU Signed-off-by: Wojciech Zmuda --- arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi | 272 +++++++++++++++++++++++ arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 + 2 files changed, 274 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi new file mode 100644 index 000000000000..8b7579ad89cc --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * dtsi for Xilinx Ultrascale+ MPSoC CoreSight components + * + * Copyright (C) 2019-2020 N7 Space Sp. z o.o. + * + * Author: Wojciech Zmuda + * + */ +/ { + etm0@fec40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xfec40000 0 0x1000>; + cpu = <&cpu0>; + clocks = <&clk100>; + clock-names = "apb_pclk"; + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&funnel1_in_port0>; + }; + }; + }; + }; + + etm1@fed40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xfed40000 0 0x1000>; + cpu = <&cpu1>; + clocks = <&clk100>; + clock-names = "apb_pclk"; + out-ports { + port { + etm1_out_port: endpoint { + remote-endpoint = <&funnel1_in_port1>; + }; + }; + }; + }; + + etm2@fee40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xfee40000 0 0x1000>; + cpu = <&cpu2>; + clocks = <&clk100>; + clock-names = "apb_pclk"; + out-ports { + port { + etm2_out_port: endpoint { + remote-endpoint = <&funnel1_in_port2>; + }; + }; + }; + }; + + etm3@fef40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xfef40000 0 0x1000>; + cpu = <&cpu3>; + clocks = <&clk100>; + clock-names = "apb_pclk"; + out-ports { + port { + etm3_out_port: endpoint { + remote-endpoint = <&funnel1_in_port3>; + }; + }; + }; + }; + + debug0@fec10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfec10000 0 0x1000>; + cpu = <&cpu0>; + clocks = <&clk100>; + clock-names = "apb_pclk"; + }; + + debug1@fed10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfed10000 0 0x1000>; + cpu = <&cpu1>; + clocks = <&clk100>; + clock-names = "apb_pclk"; + }; + + debug2@fee10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfee10000 0 0x1000>; + cpu = <&cpu2>; + clocks = <&clk100>; + clock-names = "apb_pclk"; + }; + + debug3@fee10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfef10000 0 0x1000>; + cpu = <&cpu3>; + clocks = <&clk100>; + clock-names = "apb_pclk"; + }; + + funnel1@fe920000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0xfe920000 0 0x1000>; + clocks = <&clk100>; + clock-names = "apb_pclk"; + in-ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + port@0 { + reg = <0x0>; + funnel1_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + port@1 { + reg = <0x1>; + funnel1_in_port1: endpoint { + remote-endpoint = <&etm1_out_port>; + }; + }; + port@2 { + reg = <0x2>; + funnel1_in_port2: endpoint { + remote-endpoint = <&etm2_out_port>; + }; + }; + port@3 { + reg = <0x3>; + funnel1_in_port3: endpoint { + remote-endpoint = <&etm3_out_port>; + }; + }; + }; + out-ports { + port { + funnel1_out_port0: endpoint { + remote-endpoint = <&etf1_in_port>; + }; + }; + }; + }; + + funnel2@fe930000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0xfe930000 0 0x1000>; + clocks = <&clk100>; + clock-names = "apb_pclk"; + in-ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + port@2 { + reg = <0x2>; + funnel2_in_port2: endpoint { + remote-endpoint = <&etf1_out_port>; + }; + }; + // Funnel2 has another input port connected to + // funnel0's output. Funnel0 gathers Cortex-R5 ETMs. + }; + out-ports { + port { + funnel2_out_port0: endpoint { + remote-endpoint = <&etf2_in_port>; + }; + }; + }; + }; + + etf1@fe940000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0xfe940000 0 0x1000>; + clocks = <&clk100>; + clock-names = "apb_pclk"; + in-ports { + port { + etf1_in_port: endpoint { + remote-endpoint = <&funnel1_out_port0>; + }; + }; + }; + out-ports { + port { + etf1_out_port: endpoint { + remote-endpoint = <&funnel2_in_port2>; + }; + }; + }; + }; + + etf2@fe950000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0xfe950000 0 0x1000>; + clocks = <&clk100>; + clock-names = "apb_pclk"; + in-ports { + port { + etf2_in_port: endpoint { + remote-endpoint = <&funnel2_out_port0>; + }; + }; + }; + out-ports { + port { + etf2_out_port: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + }; + }; + + replicator { + compatible = "arm,coresight-static-replicator"; + in-ports { + port { + replicator_in_port0: endpoint { + remote-endpoint = <&etf2_out_port>; + }; + }; + }; + out-ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + port@0 { + reg = <0x0>; + replicator_out_port0: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + port@1 { + reg = <0x1>; + replicator_out_port1: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + }; + }; + + etr@fe970000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0xfe970000 0 0x1000>; + clocks = <&clk100>; + clock-names = "apb_pclk"; + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = + <&replicator_out_port0>; + }; + }; + }; + }; + + tpiu@fe980000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0xfe980000 0 0x1000>; + clocks = <&clk100>; + clock-names = "apb_pclk"; + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = + <&replicator_out_port1>; + }; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 3c731e73903a..ca0a6b9f4445 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -12,6 +12,8 @@ * the License, or (at your option) any later version. */ +#include "zynqmp-coresight.dtsi" + / { compatible = "xlnx,zynqmp"; #address-cells = <2>;