From patchwork Sun Jan 5 10:45:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Hao X-Patchwork-Id: 206173 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12CFBC33C99 for ; Sun, 5 Jan 2020 10:46:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DDEE92465E for ; Sun, 5 Jan 2020 10:46:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="pFdgz2uZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726773AbgAEKqx (ORCPT ); Sun, 5 Jan 2020 05:46:53 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:24609 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726702AbgAEKqv (ORCPT ); Sun, 5 Jan 2020 05:46:51 -0500 X-UUID: e2bc8ee6dc254265b5b1e3f3b70a7945-20200105 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=DGmQNidlzNQc5LwY8YiBP+cNsBp8IGVfEGVlTvoknPc=; b=pFdgz2uZ7V1zo4Yv/x7kvKtd2o4M60g9bGE8U5fdzYIpObJ/yx9XExN8aKYXv8aL5WOiGI/eKPVswIAOKYqTKaiDaWgKYUsIG6HGZ/j9eYSTzngXFzg+aOU7pq6FdEX038OEPLwM15tbgreK731chEcqvWTtwqe4HVTUiP3lWbg=; X-UUID: e2bc8ee6dc254265b5b1e3f3b70a7945-20200105 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 103566578; Sun, 05 Jan 2020 18:46:47 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sun, 5 Jan 2020 18:46:22 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sun, 5 Jan 2020 18:45:17 +0800 From: Chao Hao To: Joerg Roedel , Rob Herring , Matthias Brugger CC: , , , , , , Chao Hao , Jun Yan , Cui Zhang , Yong Wu , Anan Sun Subject: [PATCH v2 07/19] iommu/mediatek: Add REG_MMU_WR_LEN reg define prepare for mt6779 Date: Sun, 5 Jan 2020 18:45:11 +0800 Message-ID: <20200105104523.31006-8-chao.hao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200105104523.31006-1-chao.hao@mediatek.com> References: <20200105104523.31006-1-chao.hao@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org When some platforms(ex:later mt6779) define has_wr_len variable, we need to set REG_MMU_WR_LEN to improve performance. So we add REG_MMU_WR_LEN register define in this patch. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 11 +++++++++++ drivers/iommu/mtk_iommu.h | 2 ++ 2 files changed, 13 insertions(+) -- 2.18.0 diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 5de13ab1094e..ad5690350d6a 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -44,6 +44,8 @@ #define REG_MMU_MISC_CTRL 0x048 #define REG_MMU_DCM_DIS 0x050 +#define REG_MMU_WR_LEN 0x054 +#define F_MMU_WR_THROT_DIS (BIT(5) | BIT(21)) #define REG_MMU_CTRL_REG 0x110 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) @@ -595,6 +597,13 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) } writel_relaxed(0, data->base + REG_MMU_DCM_DIS); + if (data->plat_data->has_wr_len) { + /* write command throttling mode */ + regval = readl_relaxed(data->base + REG_MMU_WR_LEN); + regval &= ~F_MMU_WR_THROT_DIS; + writel_relaxed(regval, data->base + REG_MMU_WR_LEN); + } + if (data->plat_data->reset_axi) writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); @@ -743,6 +752,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev) struct mtk_iommu_suspend_reg *reg = &data->reg; void __iomem *base = data->base; + reg->wr_len = readl_relaxed(base + REG_MMU_WR_LEN); reg->standard_axi_mode = readl_relaxed(base + REG_MMU_MISC_CTRL); reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); @@ -768,6 +778,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev) dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); return ret; } + writel_relaxed(reg->wr_len, base + REG_MMU_WR_LEN); writel_relaxed(reg->standard_axi_mode, base + REG_MMU_MISC_CTRL); writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index d4495230c6e7..0623f199e96f 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -25,6 +25,7 @@ struct mtk_iommu_suspend_reg { u32 int_main_control; u32 ivrp_paddr; u32 vld_pa_rng; + u32 wr_len; }; enum mtk_iommu_plat { @@ -43,6 +44,7 @@ struct mtk_iommu_plat_data { bool has_sub_comm[2]; bool has_vld_pa_rng; bool reset_axi; + bool has_wr_len; u32 m4u1_mask; u32 inv_sel_reg; unsigned char larbid_remap[2][MTK_LARB_NR_MAX];