From patchwork Sun Jan 5 10:45:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Hao X-Patchwork-Id: 206168 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3E92C33C99 for ; Sun, 5 Jan 2020 10:47:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A67FE207FD for ; Sun, 5 Jan 2020 10:47:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Wt5c9fV2" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727218AbgAEKr1 (ORCPT ); Sun, 5 Jan 2020 05:47:27 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:61073 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727200AbgAEKr0 (ORCPT ); Sun, 5 Jan 2020 05:47:26 -0500 X-UUID: 6aa44d3c98c74eeb9f0c1e78ab4293ac-20200105 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=3mbq9FpjSxSDLEY2w5X2s9Gfj1UKMBPHT8u/FwCDfyk=; b=Wt5c9fV25mF/KFJFOc5ImE3zvuehaP/tlV0EzygatHO1BspQwiF2nPZbJLb6Fkf8yLHOT/A4f7ZL8m7Fc2SmEaFcli4OgBqE+G4dSPduxiVx99Hhvmcs6SLNoJhbKdtMiR339KQwiphmQWMBq5J7E3YWZKscjL8LllIn+4aqU2c=; X-UUID: 6aa44d3c98c74eeb9f0c1e78ab4293ac-20200105 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1127711607; Sun, 05 Jan 2020 18:47:22 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sun, 5 Jan 2020 18:46:54 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sun, 5 Jan 2020 18:45:52 +0800 From: Chao Hao To: Joerg Roedel , Rob Herring , Matthias Brugger CC: , , , , , , Chao Hao , Jun Yan , Cui Zhang , Yong Wu , Anan Sun Subject: [PATCH v2 19/19] iommu/mediatek: Add multiple mtk_iommu_domain support for mt6779 Date: Sun, 5 Jan 2020 18:45:23 +0800 Message-ID: <20200105104523.31006-20-chao.hao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200105104523.31006-1-chao.hao@mediatek.com> References: <20200105104523.31006-1-chao.hao@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For mt6779, it need to support three mtk_iommu_domains, every mtk_iommu_domain's iova space is different. Three mtk_iommu_domains is as below: 1. Normal mtk_iommu_domain exclude 0x4000_0000~0x47ff_ffff and 0x7da0_0000~7fbf_ffff. 2. CCU mtk_iommu_domain include 0x4000_0000~0x47ff_ffff. 3. VPU mtk_iommu_domain 0x7da0_0000~0x7fbf_ffff. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 45 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 43 insertions(+), 2 deletions(-) -- 2.18.0 diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index ab09f435d437..d56254883541 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -134,6 +134,30 @@ const struct mtk_domain_data single_dom = { .max_iova = DMA_BIT_MASK(32) }; +/* + * related file: mt6779-larb-port.h + */ +const struct mtk_domain_data mt6779_multi_dom[] = { + /* normal domain */ + { + .min_iova = 0x0, + .max_iova = DMA_BIT_MASK(32), + }, + /* ccu domain */ + { + .min_iova = 0x40000000, + .max_iova = 0x48000000 - 1, + .port_mask = {MTK_M4U_ID(9, 21), MTK_M4U_ID(9, 22), + MTK_M4U_ID(12, 0), MTK_M4U_ID(12, 1)} + }, + /* vpu domain */ + { + .min_iova = 0x7da00000, + .max_iova = 0x7fc00000 - 1, + .port_mask = {MTK_M4U_ID(13, 0)} + } +}; + static struct mtk_iommu_pgtable *share_pgtable; static const struct iommu_ops mtk_iommu_ops; @@ -1050,6 +1074,21 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = { SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume) }; +static const struct mtk_iommu_resv_iova_region mt6779_iommu_rsv_list[] = { + { + .dom_id = 0, + .iova_base = 0x40000000, /* CCU */ + .iova_size = 0x8000000, + .type = IOMMU_RESV_RESERVED, + }, + { + .dom_id = 0, + .iova_base = 0x7da00000, /* VPU/MDLA */ + .iova_size = 0x2700000, + .type = IOMMU_RESV_RESERVED, + }, +}; + static const struct mtk_iommu_plat_data mt2712_data = { .m4u_plat = M4U_MT2712, .has_4gb_mode = true, @@ -1063,8 +1102,10 @@ static const struct mtk_iommu_plat_data mt2712_data = { static const struct mtk_iommu_plat_data mt6779_data = { .m4u_plat = M4U_MT6779, - .dom_cnt = 1, - .dom_data = &single_dom, + .resv_cnt = ARRAY_SIZE(mt6779_iommu_rsv_list), + .resv_region = mt6779_iommu_rsv_list, + .dom_cnt = ARRAY_SIZE(mt6779_multi_dom), + .dom_data = mt6779_multi_dom, .larbid_remap[0] = {0, 1, 2, 3, 5, 7, 10, 9}, /* vp6a, vp6b, mdla/core2, mdla/edmc*/ .larbid_remap[1] = {2, 0, 3, 1},