From patchwork Sun Jan 5 10:45:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Hao X-Patchwork-Id: 206170 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC482C33C9B for ; Sun, 5 Jan 2020 10:47:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B3EF721775 for ; Sun, 5 Jan 2020 10:47:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="MqMWF4yq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727103AbgAEKrO (ORCPT ); Sun, 5 Jan 2020 05:47:14 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:12685 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727025AbgAEKrO (ORCPT ); Sun, 5 Jan 2020 05:47:14 -0500 X-UUID: 5bf3b63f330444bfa9e261eede22e1b7-20200105 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=BU3FHHq8lyI4GErrRVuqeiEhzwtLbu5dCFfMXEQDW1k=; b=MqMWF4yqiWhgMsbK53C3+P3W1eBxvElV/CXXkEw03l+esiqkv78SUOxUtGSxx1c0RViWO/gGPSAYam1uJPrfxgplbmxWpcPe07/O5JBfuGlaqZFrk3LU5PD/ViMpYAMQkeIdFIQZeCFyBOy6769EvpwkIQSfG3AJTfsKGdtDlcU=; X-UUID: 5bf3b63f330444bfa9e261eede22e1b7-20200105 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1428780349; Sun, 05 Jan 2020 18:47:10 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sun, 5 Jan 2020 18:46:44 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sun, 5 Jan 2020 18:45:40 +0800 From: Chao Hao To: Joerg Roedel , Rob Herring , Matthias Brugger CC: , , , , , , Chao Hao , Jun Yan , Cui Zhang , Yong Wu , Anan Sun Subject: [PATCH v2 14/19] iommu/mediatek: Add mtk_domain_data structure Date: Sun, 5 Jan 2020 18:45:18 +0800 Message-ID: <20200105104523.31006-15-chao.hao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200105104523.31006-1-chao.hao@mediatek.com> References: <20200105104523.31006-1-chao.hao@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add mtk_domain_data structure to describe how many iova regions there are and the relevant the start and end address of each iova region. The number of iova region is equal to the number of mtk_iommu_domain. So we will use mtk_domain_data to initialize the start and end iova of mtk_iommu_domain. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 17 +++++++++++++++-- drivers/iommu/mtk_iommu.h | 17 +++++++++++++++++ 2 files changed, 32 insertions(+), 2 deletions(-) -- 2.18.0 diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index f2137033ec59..b1ce0a2df583 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -122,6 +122,12 @@ struct mtk_iommu_pgtable { struct io_pgtable_ops *iop; struct device *init_dev; struct list_head m4u_dom_v2; + const struct mtk_domain_data *dom_region; +}; + +const struct mtk_domain_data single_dom = { + .min_iova = 0x0, + .max_iova = DMA_BIT_MASK(32) }; static struct mtk_iommu_pgtable *share_pgtable; @@ -400,6 +406,7 @@ static struct mtk_iommu_pgtable *create_pgtable(struct mtk_iommu_data *data) dev_err(data->dev, "Failed to alloc io pgtable\n"); return ERR_PTR(-EINVAL); } + pgtable->dom_region = data->plat_data->dom_data; dev_info(data->dev, "%s create pgtable done\n", __func__); @@ -470,8 +477,10 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) /* Update our support page sizes bitmap */ dom->domain.pgsize_bitmap = pgtable->cfg.pgsize_bitmap; - dom->domain.geometry.aperture_start = 0; - dom->domain.geometry.aperture_end = DMA_BIT_MASK(32); + dom->domain.geometry.aperture_start = + pgtable->dom_region->min_iova; + dom->domain.geometry.aperture_end = + pgtable->dom_region->max_iova; dom->domain.geometry.force_aperture = true; list_add_tail(&dom->list, &pgtable->m4u_dom_v2); @@ -953,6 +962,7 @@ static const struct mtk_iommu_plat_data mt2712_data = { .has_bclk = true, .has_vld_pa_rng = true, .dom_cnt = 1, + .dom_data = &single_dom, .larbid_remap[0] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, .inv_sel_reg = REG_MMU_INV_SEL, }; @@ -960,6 +970,7 @@ static const struct mtk_iommu_plat_data mt2712_data = { static const struct mtk_iommu_plat_data mt6779_data = { .m4u_plat = M4U_MT6779, .dom_cnt = 1, + .dom_data = &single_dom, .larbid_remap[0] = {0, 1, 2, 3, 5, 7, 10, 9}, /* vp6a, vp6b, mdla/core2, mdla/edmc*/ .larbid_remap[1] = {2, 0, 3, 1}, @@ -976,6 +987,7 @@ static const struct mtk_iommu_plat_data mt8173_data = { .has_bclk = true, .reset_axi = true, .dom_cnt = 1, + .dom_data = &single_dom, .larbid_remap[0] = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */ .inv_sel_reg = REG_MMU_INV_SEL, }; @@ -984,6 +996,7 @@ static const struct mtk_iommu_plat_data mt8183_data = { .m4u_plat = M4U_MT8183, .reset_axi = true, .dom_cnt = 1, + .dom_data = &single_dom, .larbid_remap[0] = {0, 4, 5, 6, 7, 2, 3, 1}, .inv_sel_reg = REG_MMU_INV_SEL, }; diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index 3a1c79222d09..a38b26018abe 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -36,6 +36,22 @@ enum mtk_iommu_plat { M4U_MT8183, }; +/* + * reserved IOVA Domain for IOMMU users of HW limitation. + */ + +/* + * struct mtk_domain_data: domain configuration + * @min_iova: Start address of iova + * @max_iova: End address of iova + * Note: one user can only belong to one domain + */ + +struct mtk_domain_data { + dma_addr_t min_iova; + dma_addr_t max_iova; +}; + struct mtk_iommu_plat_data { enum mtk_iommu_plat m4u_plat; bool has_4gb_mode; @@ -51,6 +67,7 @@ struct mtk_iommu_plat_data { u32 m4u1_mask; u32 inv_sel_reg; unsigned char larbid_remap[2][MTK_LARB_NR_MAX]; + const struct mtk_domain_data *dom_data; }; struct mtk_iommu_domain;