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[209.132.180.67]) by mx.google.com with ESMTP id r22si23696115otn.192.2019.12.30.08.40.40; Mon, 30 Dec 2019 08:40:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZN7KKbIg; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726838AbfL3Qkk (ORCPT + 8 others); Mon, 30 Dec 2019 11:40:40 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:38297 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726798AbfL3Qkk (ORCPT ); Mon, 30 Dec 2019 11:40:40 -0500 Received: by mail-wm1-f67.google.com with SMTP id u2so14599522wmc.3 for ; Mon, 30 Dec 2019 08:40:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=tDhVs6CVDINJ1HNHUEVGjWNjJ7PiR8LnUgb8ARuG2ic=; b=ZN7KKbIgtPp1ekgR51IoF+SME6R9Cr0LaqNEinmblhhFSXm0TRG+mKuts2PSA0XJIR yqkrXoYJSH8zaP4MTVeZxu8+Mfa7lDjCdUl44E/Hl98IqMyE6sJbUICApQO9voVqHht7 41olQjXiASfh8zOCaxZm2XDH2txCBy6FOuGWoa59WPYcFi3MpWPoAUhKp3zUwejm2Jxy O/sz4ZT/rQL9LI/Peyt1xmHnS4QNvMbHI6/Kf15TEYbMLhiJc9iab8tZiWle96eSxrZN kBL2vBBIiWx0ECuTr103C35sFiqj57+zoY5d043X3pOB3mdBniNWEndn0uGkW9O9LRxm LTyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=tDhVs6CVDINJ1HNHUEVGjWNjJ7PiR8LnUgb8ARuG2ic=; b=bZgYUCBaCRfeXREV/8QtiV+t6Ptzrl5PfCWC7xiRNqBXX7TKjKoCoVbHeuarluompG pqeCdeOj/+/hHuOcAWscdMQHa6aJHG6HVxrJ5usk53ODWZbROxvWgi0sQOIPDIULheYX 9eeMRZQStB/fCKj85mBmQrCbYor0glzuj7CpxdUoOG+sGvrn3eskVakSulazVxV6T1O9 80XpVzxKrplFEuG8ZFODGziIUMbCq8NKv1XobMixPfPHRkYb3XGQjt88VNNXetX6qUdv VMd8z916KN3V7vCC4LZI6v1AGGplo/4F+E2wn/9LBBZvVAUocr9YUgpHVVjiQFthXaL/ vY2w== X-Gm-Message-State: APjAAAWVLOfz6eeIem7TDT/rgXYOkcCLdAcuiOTKErFksnc26sgOCQu6 TdSbml/PZE9Z2wbIHDirA/17HQ== X-Received: by 2002:a1c:4b01:: with SMTP id y1mr33726581wma.12.1577724038134; Mon, 30 Dec 2019 08:40:38 -0800 (PST) Received: from linaro.org ([2a00:23c5:6815:3901:a1cf:b00b:5683:ed40]) by smtp.gmail.com with ESMTPSA id b68sm21175605wme.6.2019.12.30.08.40.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Dec 2019 08:40:37 -0800 (PST) From: Mike Leach To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, coresight@lists.linaro.org Cc: linux-arm-msm@vger.kernel.org, mathieu.poirier@linaro.org, suzuki.poulose@arm.com, robh+dt@kernel.org, maxime@cerno.tech, liviu.dudau@arm.com, sudeep.holla@arm.com, lorenzo.pieralisi@arm.com, agross@kernel.org, Mike Leach Subject: [PATCH v7 02/15] coresight: cti: Add sysfs coresight mgmt reg access. Date: Mon, 30 Dec 2019 16:40:35 +0000 Message-Id: <20191230164035.28013-1-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Adds sysfs access to the coresight management registers. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose --- .../hwtracing/coresight/coresight-cti-sysfs.c | 53 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-priv.h | 1 + 2 files changed, 54 insertions(+) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index a832b8c6b866..507f8eb487fe 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -62,11 +62,64 @@ static struct attribute *coresight_cti_attrs[] = { NULL, }; +/* register based attributes */ + +/* macro to access RO registers with power check only (no enable check). */ +#define coresight_cti_reg(name, offset) \ +static ssize_t name##_show(struct device *dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \ + u32 val = 0; \ + pm_runtime_get_sync(dev->parent); \ + spin_lock(&drvdata->spinlock); \ + if (drvdata->config.hw_powered) \ + val = readl_relaxed(drvdata->base + offset); \ + spin_unlock(&drvdata->spinlock); \ + pm_runtime_put_sync(dev->parent); \ + return scnprintf(buf, PAGE_SIZE, "0x%x\n", val); \ +} \ +static DEVICE_ATTR_RO(name) + +/* coresight management registers */ +coresight_cti_reg(devaff0, CTIDEVAFF0); +coresight_cti_reg(devaff1, CTIDEVAFF1); +coresight_cti_reg(authstatus, CORESIGHT_AUTHSTATUS); +coresight_cti_reg(devarch, CORESIGHT_DEVARCH); +coresight_cti_reg(devid, CORESIGHT_DEVID); +coresight_cti_reg(devtype, CORESIGHT_DEVTYPE); +coresight_cti_reg(pidr0, CORESIGHT_PERIPHIDR0); +coresight_cti_reg(pidr1, CORESIGHT_PERIPHIDR1); +coresight_cti_reg(pidr2, CORESIGHT_PERIPHIDR2); +coresight_cti_reg(pidr3, CORESIGHT_PERIPHIDR3); +coresight_cti_reg(pidr4, CORESIGHT_PERIPHIDR4); + +static struct attribute *coresight_cti_mgmt_attrs[] = { + &dev_attr_devaff0.attr, + &dev_attr_devaff1.attr, + &dev_attr_authstatus.attr, + &dev_attr_devarch.attr, + &dev_attr_devid.attr, + &dev_attr_devtype.attr, + &dev_attr_pidr0.attr, + &dev_attr_pidr1.attr, + &dev_attr_pidr2.attr, + &dev_attr_pidr3.attr, + &dev_attr_pidr4.attr, + NULL, +}; + static const struct attribute_group coresight_cti_group = { .attrs = coresight_cti_attrs, }; +static const struct attribute_group coresight_cti_mgmt_group = { + .attrs = coresight_cti_mgmt_attrs, + .name = "mgmt", +}; + const struct attribute_group *coresight_cti_groups[] = { &coresight_cti_group, + &coresight_cti_mgmt_group, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 82e563cdc879..aba6b789c969 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -22,6 +22,7 @@ #define CORESIGHT_CLAIMCLR 0xfa4 #define CORESIGHT_LAR 0xfb0 #define CORESIGHT_LSR 0xfb4 +#define CORESIGHT_DEVARCH 0xfbc #define CORESIGHT_AUTHSTATUS 0xfb8 #define CORESIGHT_DEVID 0xfc8 #define CORESIGHT_DEVTYPE 0xfcc