From patchwork Wed Dec 4 17:51:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 180814 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp920518ile; Wed, 4 Dec 2019 09:53:25 -0800 (PST) X-Google-Smtp-Source: APXvYqzUB+8f4XmuypSW4W2kNkI7Bvhdf6/JMZCdBlCSJCubUFXYod+DieBnAoITdzu+0G31Gppk X-Received: by 2002:a05:6830:10a:: with SMTP id i10mr3289041otp.365.1575482005563; Wed, 04 Dec 2019 09:53:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575482005; cv=none; d=google.com; s=arc-20160816; b=UaO7ZTw+dAdvmT3NqjULo/EEfqXP+y0Bfr6aF/rVOueMDY1UsZImm/CN8gkvhk+Y94 Xi0+6KZEUGy+DDWBAnA5YHUlCh1oe3pFt/4doTZrGUqly1A1arx4srCeK94sMvSt2Gop iR0OkENntEi8PgvFgRRQmwNsyiCWBsS1/zSm0zFLXoSHAAvk4Hnb/zNin1CaUEkUCoN5 Fi8asTNI1d1mpq9Fv2lzCX/B87cxz63xVdZA4CQKyuAVp+KDftctW2wqHeu5J9+Md2DX 6QAMreS0KvISzX5SBnoGFmCrzJipb4YuIyGflOJslLqPruVZcXwI1Rz/GpE3AXXlYJ6k Yzdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=AnC853RFFoxs00i8fMk3eDa7i0nyPwZrTi1e2WCpjj8=; b=paDnVwpA8L2tiyv5EEw6buc/2QHtgtKKpKs62xy90IOscpS7AQgi3H5tGQ9JQG7kyk 2X4gkCRE8NXAjBqPuxvVMniIhmnnGhVmzyyxyXd6ne+5VP7/F3JkX0+Vap+VzO/LJJnS NA5HCBDHlCqbKCpGICfNNgFLrQD5bwkVXwxqGk7j2+6nR6Tr+xR1Sm7flreEh8H4XfRf jigzIfGROLNNrpozxosudGzwHpT6wAxlO30nqDHcxguezaNK/I9/iyW9obodOPfd6BZL VTDMscrC4ilYrmQh/rukHkwfUHtnmDawDPz3OCXspf4IlmnmYtZ603VCttRtriJuLTbX SJIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TRXATRf5; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n8si3627380otr.102.2019.12.04.09.53.25; Wed, 04 Dec 2019 09:53:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TRXATRf5; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728081AbfLDRxX (ORCPT + 8 others); Wed, 4 Dec 2019 12:53:23 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:50742 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726934AbfLDRxW (ORCPT ); Wed, 4 Dec 2019 12:53:22 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB4HrFpX079687; Wed, 4 Dec 2019 11:53:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575481995; bh=AnC853RFFoxs00i8fMk3eDa7i0nyPwZrTi1e2WCpjj8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TRXATRf5F6o/rVNB7WveJsgTC6EOTmznGk1WH/p4zF4NDAyRamYyJetXDo2rKhno6 4/ohZEpEXJPbR8fYIXHx4OGUwf5nZJZem5qYJc6gUY2hMpsGuWp/UHT1RhHp/JWQqb VtNMDs2gU38WZxfEeiZoHTqzA+5/NoG85pOMxIXk= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB4HrF2D040848 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 4 Dec 2019 11:53:15 -0600 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Wed, 4 Dec 2019 11:53:15 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Wed, 4 Dec 2019 11:53:15 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB4HrFp4034157; Wed, 4 Dec 2019 11:53:15 -0600 From: Dan Murphy To: CC: , , , Dan Murphy , Sean Nyekjaer Subject: [PATCH 2/2] net: m_can: Make wake-up gpio an optional Date: Wed, 4 Dec 2019 11:51:12 -0600 Message-ID: <20191204175112.7308-2-dmurphy@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191204175112.7308-1-dmurphy@ti.com> References: <20191204175112.7308-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The device has the ability to disable the wake-up pin option. The wake-up pin can be either force to GND or Vsup and does not have to be tied to a GPIO. In order for the device to not use the wake-up feature write the register to disable the WAKE_CONFIG option. Signed-off-by: Dan Murphy CC: Sean Nyekjaer --- drivers/net/can/m_can/tcan4x5x.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) -- 2.23.0 diff --git a/drivers/net/can/m_can/tcan4x5x.c b/drivers/net/can/m_can/tcan4x5x.c index 3db619209fe1..6e37c3fd87af 100644 --- a/drivers/net/can/m_can/tcan4x5x.c +++ b/drivers/net/can/m_can/tcan4x5x.c @@ -101,6 +101,8 @@ #define TCAN4X5X_MODE_STANDBY BIT(6) #define TCAN4X5X_MODE_NORMAL BIT(7) +#define TCAN4X5X_DISABLE_WAKE_MSK (BIT(31) | BIT(30)) + #define TCAN4X5X_SW_RESET BIT(2) #define TCAN4X5X_MCAN_CONFIGURED BIT(5) @@ -338,6 +340,15 @@ static int tcan4x5x_init(struct m_can_classdev *cdev) return ret; } +static int tcan4x5x_disable_wake(struct m_can_classdev *cdev) +{ + struct tcan4x5x_priv *tcan4x5x = cdev->device_data; + + return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG, + TCAN4X5X_DISABLE_WAKE_MSK, 0x00); + +} + static int tcan4x5x_parse_config(struct m_can_classdev *cdev) { struct tcan4x5x_priv *tcan4x5x = cdev->device_data; @@ -345,8 +356,10 @@ static int tcan4x5x_parse_config(struct m_can_classdev *cdev) tcan4x5x->device_wake_gpio = devm_gpiod_get(cdev->dev, "device-wake", GPIOD_OUT_HIGH); if (IS_ERR(tcan4x5x->device_wake_gpio)) { - dev_err(cdev->dev, "device-wake gpio not defined\n"); - return -EINVAL; + if (PTR_ERR(tcan4x5x->power) == -EPROBE_DEFER) + return -EPROBE_DEFER; + + tcan4x5x_disable_wake(cdev); } tcan4x5x->reset_gpio = devm_gpiod_get_optional(cdev->dev, "reset", @@ -428,10 +441,6 @@ static int tcan4x5x_can_probe(struct spi_device *spi) spi_set_drvdata(spi, priv); - ret = tcan4x5x_parse_config(mcan_class); - if (ret) - goto out_clk; - /* Configure the SPI bus */ spi->bits_per_word = 32; ret = spi_setup(spi); @@ -441,6 +450,10 @@ static int tcan4x5x_can_probe(struct spi_device *spi) priv->regmap = devm_regmap_init(&spi->dev, &tcan4x5x_bus, &spi->dev, &tcan4x5x_regmap); + ret = tcan4x5x_parse_config(mcan_class); + if (ret) + goto out_clk; + tcan4x5x_power_enable(priv->power, 1); ret = m_can_class_register(mcan_class);