From patchwork Thu Nov 21 05:02:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179898 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp3086048ilf; Wed, 20 Nov 2019 21:02:39 -0800 (PST) X-Google-Smtp-Source: APXvYqw3oafUXy+5YNRdxsEh2lj9CZ5oVwMOyLX1ZnVSY08AtWGl4ynX7HvsNEBQRtZTqptSPsaq X-Received: by 2002:a17:906:6006:: with SMTP id o6mr10777738ejj.51.1574312559041; Wed, 20 Nov 2019 21:02:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574312559; cv=none; d=google.com; s=arc-20160816; b=uX2DESRJiOlvK3keCLNCV6XwvZNa99jg8rSqYexKNOK+Sc1D1d4fl+LV27cefniX1H xsx6l9ibdEtbMUtq5axGRnsS5SCYJCcJN89apBrJqxecZJR6bvu2076xXnge8qpgKwei vqCf3P1svA4kNhXh/23kTaaOueBySyIOzdJFjXBHgR3mrpZzIfOliauVIwByE1aZdfPT xy8ZcWajoWQFFeSdS2XzpwdtpKEzr6YYj/yuogUr3dGi8P+6yiVjunpeSRMT8XcZtRbQ wu+eQYqKCG8s5oR7HmskXqGqX8Ifj/GDkWGNxcHcNalEfH03RW19Su4qa4YziFYd8MQC VZRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=zAnmQfc3w01ah3vUf7UYKf6AOsGkgtuUJmElCOlYrbM=; b=TtW7cweItBR0hBHrT+Gnt3inI3Z2OvjKaO1IvQr7fKr5e0Jue1Qym2bKeQegQZTzC1 ngd6c0eDS37GsQrZ912EuVLlKYjc5NyDO1p5G1RkxplLi8eVESiiFKg9aZIv8TyoDzsP X1OAWNTaNXz4O5urM8Rvx8JeqztfdGBukKlvFapL/xCazskOEmM1gOpgnuLbqpKY+fGy cTRgKqRPWsYT05ZLy6Y7mN9Iv7Hb1QVwbbZKgv7VlKke0Dj59COa1dF6NIt2eojLP943 43FcDVDpTht2AxUOXhiUTrCZkodnO/40op0vb9UH1F8SBptjXGswj9iQPne9k45blOpL Yhsg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h20si1499395edj.48.2019.11.20.21.02.38; Wed, 20 Nov 2019 21:02:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726454AbfKUFCd (ORCPT + 8 others); Thu, 21 Nov 2019 00:02:33 -0500 Received: from mx2.suse.de ([195.135.220.15]:36490 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726502AbfKUFCX (ORCPT ); Thu, 21 Nov 2019 00:02:23 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id C0F52B183; Thu, 21 Nov 2019 05:02:21 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v5 9/9] arm64: dts: realtek: rtd139x: Add irq muxes and UART interrupts Date: Thu, 21 Nov 2019 06:02:08 +0100 Message-Id: <20191121050208.11324-10-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191121050208.11324-1-afaerber@suse.de> References: <20191121050208.11324-1-afaerber@suse.de> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add iso and misc IRQ mux DT nodes for Realtek RTD1395 SoC. Update the UART DT nodes with interrupts from these muxes, so that UART0 can be used without earlycon. Signed-off-by: Andreas Färber --- v4 -> v5: Unchanged v4: New arch/arm64/boot/dts/realtek/rtd139x.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- 2.16.4 diff --git a/arch/arm64/boot/dts/realtek/rtd139x.dtsi b/arch/arm64/boot/dts/realtek/rtd139x.dtsi index 706da12f9ea3..f53cb8a5083b 100644 --- a/arch/arm64/boot/dts/realtek/rtd139x.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd139x.dtsi @@ -84,6 +84,14 @@ #reset-cells = <1>; }; + iso_irq_mux: interrupt-controller@7000 { + compatible = "realtek,rtd1395-iso-irq-mux"; + reg = <0x7000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + iso_reset: reset-controller@7088 { compatible = "snps,dw-low-reset"; reg = <0x7088 0x4>; @@ -103,6 +111,8 @@ reg-io-width = <4>; clock-frequency = <27000000>; resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; + interrupt-parent = <&iso_irq_mux>; + interrupts = <2>; status = "disabled"; }; @@ -111,6 +121,14 @@ reg = <0x1a200 0x8>; }; + misc_irq_mux: interrupt-controller@1b000 { + compatible = "realtek,rtd1395-misc-irq-mux"; + reg = <0x1b000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + uart1: serial@1b200 { compatible = "snps,dw-apb-uart"; reg = <0x1b200 0x100>; @@ -118,6 +136,8 @@ reg-io-width = <4>; clock-frequency = <432000000>; resets = <&reset2 RTD1295_RSTN_UR1>; + interrupt-parent = <&misc_irq_mux>; + interrupts = <3>; status = "disabled"; }; @@ -128,6 +148,8 @@ reg-io-width = <4>; clock-frequency = <432000000>; resets = <&reset2 RTD1295_RSTN_UR2>; + interrupt-parent = <&misc_irq_mux>; + interrupts = <8>; status = "disabled"; }; };