From patchwork Sun Nov 17 07:21:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179565 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp1380426ilf; Sat, 16 Nov 2019 23:21:35 -0800 (PST) X-Google-Smtp-Source: APXvYqzycqyGBfK7hT0zrg4R06Tk3dxwRCTy2huQAon4iTGVXa+PAykZjfCbyD4A0aXf5ApBH1g3 X-Received: by 2002:a17:906:b30c:: with SMTP id n12mr15860210ejz.96.1573975295052; Sat, 16 Nov 2019 23:21:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573975295; cv=none; d=google.com; s=arc-20160816; b=DIMD99xl6+CbDdcXOh3uFOwazbA09VXitdybY8UnNlkN/jJpOd2pGEVkZFOAzAELB8 eSlBurcanSQAp1MCy0tDOl73FIxvbAUK569W9U6SOUQDbwZ/nNHTwZbKzvL3dCv0rqF/ zszY8atj6bBmBsLanWj5w4GcCQSufIOxIo3or/oWIbX7qhjkcoE9agq+xsQOzyaBe0Ph n5eOJs9CV0asDyst+jNxxANNINrJoAJsTwzvaPvqzhnSPLThCrOhvzEKc/frnt+qlZrZ 6VzBUemmPYM5OtHUPqIGIIgCNafytflr4QeiEVzcVrDi7WIxrYmUrmJdxw/z4gKonWZz WIfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=ChWcO3zaE8PgvaexPPqf8GDV0G0s2CzmNdnomhtaZT8=; b=YSjMOP07YXh3RGbtpU2D8NmzIjuSqSv6gk6D1ung7qLS1tAKMVhPeRlEj/SRfgsSp8 MEx4L742Cco5tp+IiQFysHVL5DAQi1GjVO45b1QGNg+glvMNCmjaQvbMDrMwf7oxk7tt HmOdSWhATpRnll9BjDECB7pq/XUWfOSCXdTIq+hL6uVHhzHLh0ROeoX6W1niQcgKcRWT 7GA07b6qTgSnc52HaLkigQWyqRlZyGODjEIT8fxZtfdHI7ID5g63b319IKIy1xIhJG0a ESI0UQS2FuFXvS0WyBuEI52FEsCV+Gx/qVkSyub+BQs9BAy/0LDDqJ0bLFjU7J7mvc7a x/UA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q20si9182013eja.339.2019.11.16.23.21.34; Sat, 16 Nov 2019 23:21:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726174AbfKQHVY (ORCPT + 8 others); Sun, 17 Nov 2019 02:21:24 -0500 Received: from mx2.suse.de ([195.135.220.15]:40790 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725901AbfKQHVX (ORCPT ); Sun, 17 Nov 2019 02:21:23 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 6C145B2FD; Sun, 17 Nov 2019 07:21:21 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Philipp Zabel , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v3 5/8] dt-bindings: reset: Add Realtek RTD1195 Date: Sun, 17 Nov 2019 08:21:06 +0100 Message-Id: <20191117072109.20402-6-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191117072109.20402-1-afaerber@suse.de> References: <20191117072109.20402-1-afaerber@suse.de> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a header with symbolic reset indices for Realtek RTD1195 SoC. Naming was derived from BSP register description headers. Acked-by: Philipp Zabel Reviewed-by: Rob Herring Signed-off-by: Andreas Färber --- v3: Unchanged from RTD1295 reset v2 include/dt-bindings/reset/realtek,rtd1195.h | 74 +++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 include/dt-bindings/reset/realtek,rtd1195.h -- 2.16.4 diff --git a/include/dt-bindings/reset/realtek,rtd1195.h b/include/dt-bindings/reset/realtek,rtd1195.h new file mode 100644 index 000000000000..27902abf935b --- /dev/null +++ b/include/dt-bindings/reset/realtek,rtd1195.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ +/* + * Realtek RTD1195 reset controllers + * + * Copyright (c) 2017 Andreas Färber + */ +#ifndef DT_BINDINGS_RESET_RTD1195_H +#define DT_BINDINGS_RESET_RTD1195_H + +/* soft reset 1 */ +#define RTD1195_RSTN_MISC 0 +#define RTD1195_RSTN_RNG 1 +#define RTD1195_RSTN_USB3_POW 2 +#define RTD1195_RSTN_GSPI 3 +#define RTD1195_RSTN_USB3_P0_MDIO 4 +#define RTD1195_RSTN_VE_H265 5 +#define RTD1195_RSTN_USB 6 +#define RTD1195_RSTN_USB_PHY0 8 +#define RTD1195_RSTN_USB_PHY1 9 +#define RTD1195_RSTN_HDMIRX 11 +#define RTD1195_RSTN_HDMI 12 +#define RTD1195_RSTN_ETN 14 +#define RTD1195_RSTN_AIO 15 +#define RTD1195_RSTN_GPU 16 +#define RTD1195_RSTN_VE_H264 17 +#define RTD1195_RSTN_VE_JPEG 18 +#define RTD1195_RSTN_TVE 19 +#define RTD1195_RSTN_VO 20 +#define RTD1195_RSTN_LVDS 21 +#define RTD1195_RSTN_SE 22 +#define RTD1195_RSTN_DCU 23 +#define RTD1195_RSTN_DC_PHY 24 +#define RTD1195_RSTN_CP 25 +#define RTD1195_RSTN_MD 26 +#define RTD1195_RSTN_TP 27 +#define RTD1195_RSTN_AE 28 +#define RTD1195_RSTN_NF 29 +#define RTD1195_RSTN_MIPI 30 + +/* soft reset 2 */ +#define RTD1195_RSTN_ACPU 0 +#define RTD1195_RSTN_VCPU 1 +#define RTD1195_RSTN_PCR 9 +#define RTD1195_RSTN_CR 10 +#define RTD1195_RSTN_EMMC 11 +#define RTD1195_RSTN_SDIO 12 +#define RTD1195_RSTN_I2C_5 18 +#define RTD1195_RSTN_RTC 20 +#define RTD1195_RSTN_I2C_4 23 +#define RTD1195_RSTN_I2C_3 24 +#define RTD1195_RSTN_I2C_2 25 +#define RTD1195_RSTN_I2C_1 26 +#define RTD1195_RSTN_UR1 28 + +/* soft reset 3 */ +#define RTD1195_RSTN_SB2 0 + +/* iso soft reset */ +#define RTD1195_ISO_RSTN_VFD 0 +#define RTD1195_ISO_RSTN_IR 1 +#define RTD1195_ISO_RSTN_CEC0 2 +#define RTD1195_ISO_RSTN_CEC1 3 +#define RTD1195_ISO_RSTN_DP 4 +#define RTD1195_ISO_RSTN_CBUSTX 5 +#define RTD1195_ISO_RSTN_CBUSRX 6 +#define RTD1195_ISO_RSTN_EFUSE 7 +#define RTD1195_ISO_RSTN_UR0 8 +#define RTD1195_ISO_RSTN_GMAC 9 +#define RTD1195_ISO_RSTN_GPHY 10 +#define RTD1195_ISO_RSTN_I2C_0 11 +#define RTD1195_ISO_RSTN_I2C_6 12 +#define RTD1195_ISO_RSTN_CBUS 13 + +#endif