From patchwork Tue Nov 12 14:33:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 179194 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp7824273ocf; Tue, 12 Nov 2019 06:32:24 -0800 (PST) X-Google-Smtp-Source: APXvYqwdqL8juLBvtrBcDt+54BIYcUgJiEbN2IR0ajkusJCSp2n9EdnHLRjPv9CW2z6pMjWoocpN X-Received: by 2002:a17:906:6dd1:: with SMTP id j17mr8662587ejt.86.1573569144536; Tue, 12 Nov 2019 06:32:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573569144; cv=none; d=google.com; s=arc-20160816; b=Mk7JBgKQncj2nJ+/eQ3vPl1dxqGkiHPA1LWBxvB31mEgOxCrvOh96C46g0bJV9h8Mo X25Af6JJ4psJz8bThvoGlyjhwQhOBS1UbKhwvEbHvZV7uSphDiHKKPFlPZHyG0IFfG5+ 9MMBmyuv71UVPYIA0ZTxRzwdVtdvkEJa9Rpz6Id61HWUTe058pujef6rmOWgzWqJGJkm Qzfj2rRLojj/6P+rMIt/W7f63OKasjxW/m3CkqkX3wPgwSaeEOP+yLAQ8Lp3kdKOH+EN ZJifFhRinr4FQMPV+IOzaI0yX/50QYPPBu3C6P1qGKL1urcbGuS+WXtle5g2GbYj/Kwd O3+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=64Xdsa4GcScCQ6gsuttCG1TPeRNHSov0ioT0JBvdRY0=; b=UsVGNecC7WU/lMdSOu5FOrSgrRoSRGI/tDLS27SkpIPMGn6WwogMkuDSIIh9dCvfVF TtKQl9vqEwXEzj1qoeLNS32vytma+Vu9rszbfKMXP9CNqRaG5uy8H44JQ2zosET7W0Fd Z5M6eikpbzRXhueq84+e2UoLvSVwOVDN/exwOQR/zu81+3b+pplaS2vPYywbg2heGguw QWUJsJesbQTjsuwJJtLYLG5uAH0S2+3tjs5GFrDfRbTXfBW4azHKYiQAOvPEGgXbXGSJ m1Mk2w+6LPOF0UkmqP8w3CCoA0WA7nyqEjHGhyaN7i7/MCCXQ6Gl54d9uvybOLk9dEYt faew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=C3nYqYVr; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s7si14849393eds.215.2019.11.12.06.32.24; Tue, 12 Nov 2019 06:32:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=C3nYqYVr; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727986AbfKLOcW (ORCPT + 8 others); Tue, 12 Nov 2019 09:32:22 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37818 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727976AbfKLOcW (ORCPT ); Tue, 12 Nov 2019 09:32:22 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id xACEWFkH014908; Tue, 12 Nov 2019 08:32:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1573569135; bh=64Xdsa4GcScCQ6gsuttCG1TPeRNHSov0ioT0JBvdRY0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=C3nYqYVrm0DVlYGLE313wG7C/zUS8+Q52/bYEooo7AeDddYHU/j8IGAztxVTyd635 wDFtH/Gu0zWu5hFphHgV7jVF3o2aAb4CeEPD3t2Rj/c6k+IiBqSf4JW9ykJ9UuKd1d 6EoSOwAysgiw60fzXkIZg54b9hq5wg27qnKoIE5M= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id xACEWFFf042736; Tue, 12 Nov 2019 08:32:15 -0600 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Tue, 12 Nov 2019 08:31:57 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Tue, 12 Nov 2019 08:31:57 -0600 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xACEVjUR050451; Tue, 12 Nov 2019 08:32:12 -0600 From: Peter Ujfalusi To: , CC: , , , , Subject: [PATCH 8/9] arm64: dts: ti: k3-j721e: DMA support Date: Tue, 12 Nov 2019 16:33:00 +0200 Message-ID: <20191112143301.3168-9-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191112143301.3168-1-peter.ujfalusi@ti.com> References: <20191112143301.3168-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the ringacc and udmap nodes for main and mcu NAVSS. Signed-off-by: Peter Ujfalusi --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 40 +++++++++++++++++ .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 45 +++++++++++++++++++ 2 files changed, 85 insertions(+) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 4bf8c27ecc64..66583625dc95 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -56,6 +56,10 @@ cbass_main_navss: navss@30000000 { #address-cells = <2>; #size-cells = <2>; ranges; + dma-coherent; + dma-ranges; + + ti,sci-dev-id = <199>; main_navss_intr: interrupt-controller1 { compatible = "ti,sci-intr"; @@ -214,6 +218,42 @@ mailbox0_cluster11: mailbox@31f8b000 { ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; }; + + main_ringacc: ringacc@3c000000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x3c000000 0x0 0x400000>, + <0x0 0x38000000 0x0 0x400000>, + <0x0 0x31120000 0x0 0x100>, + <0x0 0x33000000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + ti,num-rings = <1024>; + ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ + ti,sci = <&dmsc>; + ti,sci-dev-id = <211>; + msi-parent = <&main_udmass_inta>; + }; + + main_udmap: dma-controller@31150000 { + compatible = "ti,j721e-navss-main-udmap"; + reg = <0x0 0x31150000 0x0 0x100>, + <0x0 0x34000000 0x0 0x100000>, + <0x0 0x35000000 0x0 0x100000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <1>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <212>; + ti,ringacc = <&main_ringacc>; + + ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ + <0x0f>, /* TX_HCHAN */ + <0x10>; /* TX_UHCHAN */ + ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ + <0x0b>, /* RX_HCHAN */ + <0x0c>; /* RX_UHCHAN */ + ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ + }; }; main_pmx0: pinmux@11c000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 555dc7b7aedc..13c0e6953d33 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -121,4 +121,49 @@ wkup_gpio1: gpio@42100000 { clocks = <&k3_clks 114 0>; clock-names = "gpio"; }; + + cbass_mcu_navss: navss@28380000 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-coherent; + dma-ranges; + + ti,sci-dev-id = <232>; + + mcu_ringacc: ringacc@2b800000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + ti,num-rings = <286>; + ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ + ti,sci = <&dmsc>; + ti,sci-dev-id = <235>; + msi-parent = <&main_udmass_inta>; + }; + + mcu_udmap: udmap@285c0000 { + compatible = "ti,j721e-navss-mcu-udmap"; + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x2aa00000 0x0 0x40000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <1>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <236>; + ti,ringacc = <&mcu_ringacc>; + + ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ + <0x0f>; /* TX_HCHAN */ + ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ + <0x0b>; /* RX_HCHAN */ + ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ + }; + }; };