From patchwork Mon Nov 11 13:53:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 179067 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp6372203ocf; Mon, 11 Nov 2019 05:52:39 -0800 (PST) X-Google-Smtp-Source: APXvYqw6bjXjEfttMTWGNkFVhqpv0B5wtmXd3WktW37vLS9vqvFBOn7fDTXD3N7dsQlHZrxfp6Ap X-Received: by 2002:aa7:c145:: with SMTP id r5mr26838731edp.102.1573480359694; Mon, 11 Nov 2019 05:52:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573480359; cv=none; d=google.com; s=arc-20160816; b=gIdJ66z6f/hVsdT+p1LGbZB5SnOeKWbwp8MhoEtbzRStBtAlp2NSxfID4Lrw6lGX4s Xd6HM/8h9PbCKP9BDwAdUPNuXMaoyCV+pXbog+MCCkwwYvb7iX8rI2TtBIfzezEdxEUU +54NSQDi4rrrXuXJlAJtRjUdnCcSHWAs73WpFlIXVWTk/4K9BVi34TFPCDMy0mTl6AM6 66Gru0ssIBqIWmYa8msdW2moTtPC1egqLIaePg1rYByqQjPOJ6xhaItJUCF69eVoa+8e HnkHhEvHQ9BsQ+j0rlmnEkex70NEu2x2AfXXLCsDxALdnBtURTrLwCGX94XKxQJpggf3 JpSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=EeH349x8o4SCZvve2w+07qwX2Rkls7hx3AcZBuQt9LU=; b=ijsoAun4JqZpXHWgNVgeZ/mJ8wu/aJKvYmBkTBqCwkluHV+7TFmJwkx2+hSsj+oCVQ G2cYKsVsLVrI52NAhg2/4ZNErVMUoXu4PYf2Wtn9DBWADWfoRI+19jvZe+vWpvJKhmNx IcaZomIWO1/v0zwa68xzSm41Qbm03xdV2bqusfYmeCYJK0DUDXVWT/K5iTzlC5c2jIAl ZL+1lbtLdJG1RhX5VRloj925RmLxc3J/WWv026mLJBJDkCRFGgWa33z2S/Qg+eFqvwuV cDM4ZFWmqPU+4Q+ZjATWrhqlWZVvUQ6xAQnlqd0kk2JCsVwe2sjVfvLLZ5qYS1zM7Z5Z 6OAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="KqBq/xVw"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f6si11349486edl.442.2019.11.11.05.52.39; Mon, 11 Nov 2019 05:52:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="KqBq/xVw"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727010AbfKKNwj (ORCPT + 8 others); Mon, 11 Nov 2019 08:52:39 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:43394 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726902AbfKKNwi (ORCPT ); Mon, 11 Nov 2019 08:52:38 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xABDqNMI013767; Mon, 11 Nov 2019 07:52:23 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1573480344; bh=EeH349x8o4SCZvve2w+07qwX2Rkls7hx3AcZBuQt9LU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=KqBq/xVwwMTtbYDNVMqK7NlSPdl+2LAogK/L+EtCT/M6+3t8OW6iR1cBZqQGoe8we YbWSA0Vl3unsoTtwxAiqO0/gCR5aaCld/wiRh3eglpm+cOUAomp+rysuaL3kcZeGeZ hR/fecFRpNfVTS/q5Wk6fwEAX0vnLIkk4igPo6ok= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xABDqNY6001101 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 11 Nov 2019 07:52:23 -0600 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 11 Nov 2019 07:52:05 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 11 Nov 2019 07:52:05 -0600 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id xABDqE8m097668; Mon, 11 Nov 2019 07:52:19 -0600 From: Peter Ujfalusi To: , , , CC: , , , , , , , , , Subject: [PATCH v5 01/15] bindings: soc: ti: add documentation for k3 ringacc Date: Mon, 11 Nov 2019 15:53:16 +0200 Message-ID: <20191111135330.8235-2-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191111135330.8235-1-peter.ujfalusi@ti.com> References: <20191111135330.8235-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Grygorii Strashko The Ring Accelerator (RINGACC or RA) provides hardware acceleration to enable straightforward passing of work between a producer and a consumer. There is one RINGACC module per NAVSS on TI AM65x and j721e. This patch introduces RINGACC device tree bindings. Signed-off-by: Grygorii Strashko Signed-off-by: Peter Ujfalusi Reviewed-by: Rob Herring --- .../devicetree/bindings/soc/ti/k3-ringacc.txt | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt new file mode 100644 index 000000000000..59758ccce809 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt @@ -0,0 +1,59 @@ +* Texas Instruments K3 NavigatorSS Ring Accelerator + +The Ring Accelerator (RA) is a machine which converts read/write accesses +from/to a constant address into corresponding read/write accesses from/to a +circular data structure in memory. The RA eliminates the need for each DMA +controller which needs to access ring elements from having to know the current +state of the ring (base address, current offset). The DMA controller +performs a read or write access to a specific address range (which maps to the +source interface on the RA) and the RA replaces the address for the transaction +with a new address which corresponds to the head or tail element of the ring +(head for reads, tail for writes). + +The Ring Accelerator is a hardware module that is responsible for accelerating +management of the packet queues. The K3 SoCs can have more than one RA instances + +Required properties: +- compatible : Must be "ti,am654-navss-ringacc"; +- reg : Should contain register location and length of the following + named register regions. +- reg-names : should be + "rt" - The RA Ring Real-time Control/Status Registers + "fifos" - The RA Queues Registers + "proxy_gcfg" - The RA Proxy Global Config Registers + "proxy_target" - The RA Proxy Datapath Registers +- ti,num-rings : Number of rings supported by RA +- ti,sci-rm-range-gp-rings : TI-SCI RM subtype for GP ring range +- ti,sci : phandle on TI-SCI compatible System controller node +- ti,sci-dev-id : TI-SCI device id of the ring accelerator +- msi-parent : phandle for "ti,sci-inta" interrupt controller + +Optional properties: + -- ti,dma-ring-reset-quirk : enable ringacc / udma ring state interoperability + issue software w/a + +Example: + +ringacc: ringacc@3c000000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x3c000000 0x0 0x400000>, + <0x0 0x38000000 0x0 0x400000>, + <0x0 0x31120000 0x0 0x100>, + <0x0 0x33000000 0x0 0x40000>; + reg-names = "rt", "fifos", + "proxy_gcfg", "proxy_target"; + ti,num-rings = <818>; + ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ + ti,dma-ring-reset-quirk; + ti,sci = <&dmsc>; + ti,sci-dev-id = <187>; + msi-parent = <&inta_main_udmass>; +}; + +client: + +dma_ipx: dma_ipx@ { + ... + ti,ringacc = <&ringacc>; + ... +}