From patchwork Fri Nov 8 15:25:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 178919 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2860881ilf; Fri, 8 Nov 2019 07:27:01 -0800 (PST) X-Google-Smtp-Source: APXvYqyYY1pgblz6JTf/xgyqiTRFStvhRqNOgPpgJouW6wKbJNUH2VouUMsxcgOOzznbPmgU/9lU X-Received: by 2002:aa7:d2cf:: with SMTP id k15mr10769585edr.267.1573226821507; Fri, 08 Nov 2019 07:27:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573226821; cv=none; d=google.com; s=arc-20160816; b=GtWTjCGasgMxGR0kO7J7OmOQMPcls57zyT5/peihoFNbT0N+LW+VQaiAlXqTtYyAtF a7oXSc/WFm2uEvUtaGLj71LVjlX6DqYScZma6aYWIs0hyrZKnU4tMSAFfyu44fOggKs7 abmBbOVqh9aUpIDKenNpiaLdXRbQY654HYvf0aJlTtiDVUy07qESddAUVBLxSO3u1EGw 1KV8CM3Vm8lvgQINmmgj1eBt1cPqhEt0la0nM1pNBE/QI7VeQAN/hs+u7bv7pCfd8Qpa jRAr/ghUKZVuSo42YPoEvTzSa5ojQXdLefg+1AuNUVL/TR9rx8KbpnmDoARAc8OxnCIb GN1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FjGV9dHEsXE/CXRMwyPeo6zW+qyz6ot3r0JcxY8EA5E=; b=GPdCbHEkwoeCSdt8afTlPaFJReeHCHXu7+bKfKVw5D31j7ZtBmgUMqamx6N0HgCYE4 bdiaDfCZebGNl8KoT88ofI8bbgc1Jf2Wwl9M/iKWxTNDtPC/DGJVLw0EsKfTViGyARjQ Dja1Ip06RH0Uns06hs4nFlePexgC0dKM1r0AzCDljgL6OwSck++7eJUzwhBsSosZXzCR n4I554rqMT+VGHh0kr3+NiYgQ/qPDT+4TJfZGzE0w7wxe+VbApqqzc4Gau6k3FjZqgmS 51uygrEnn3594mcr53lWA1ACVh+Tp20UIvY+cARY5YMjP5qUKQKH9KGr1TXGKcZF0Gre 7lRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Stc/zRTg"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y31si4384892edb.47.2019.11.08.07.27.01; Fri, 08 Nov 2019 07:27:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Stc/zRTg"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726845AbfKHP1A (ORCPT + 8 others); Fri, 8 Nov 2019 10:27:00 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:34600 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726743AbfKHP1A (ORCPT ); Fri, 8 Nov 2019 10:27:00 -0500 Received: by mail-wr1-f66.google.com with SMTP id e6so7561545wrw.1 for ; Fri, 08 Nov 2019 07:26:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FjGV9dHEsXE/CXRMwyPeo6zW+qyz6ot3r0JcxY8EA5E=; b=Stc/zRTgvuJV42ldqRHlqe8DkziQ/xZI3K/M//32mxdJaRU1jz2L5/fMxZ1QFhpcGb EvSLry3iFu8329VB2GuTsvuMtRKQtUr6NhZe+OfFoUtq8NdYCPynlIwHbw/GjFUbmRC+ H6gal8DBpakRVo3SnhTJfseRLFp1XqfFkb3D3NUiwdPCcqFJAIgPj+gGr6Z9Up4EP+4P 8+Ut1quAnJxAurGbZKQH/VrQGWCWm7la8zmxc89J8tDCxR4MRqdAj9qnVky2l9P/QGSc 7hQrDyjXx2qQgCLFiaNFaKInDn2CY6ehhHcEYqTjArSQZFKJgu0xbSGyle/kTSvYSm0a jagQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FjGV9dHEsXE/CXRMwyPeo6zW+qyz6ot3r0JcxY8EA5E=; b=VCqo/qeaLZ3m1fEd0qhjkA4Lwt7kfUCdkUI9A8QTB+8YsqOSRRVaGwVddGpDrF41b0 XSXJ+rc0ImOLluSmaEY/J72KaNBrnsBjkLOsfymnt/HtRVTDSX9ln2To6G7vaqxjZzLi OjSVeEznACiX3WJa/bspJUfzYiZNdNmyecR0uTszA1Qds14WWuxhDfJ0DWLDD7EQF+Sd fndiRizAPH+mpl7lid/XRCo9nP5qXGFDDvOILnarAPcanbvpIOjq9UNsV7mHP+5eAYrJ HrRTBv+U+FhbKTktstCPBY5eE1MCspJ9APETEgN0T2XYQKQAwIKD83Wk0n8HCTTTFQtc 4lFw== X-Gm-Message-State: APjAAAVj/IV2Kl2kHL6WKhobpNCY2p+u2yIXnjn/vXtfAJuYobPPxnD0 ZzJ+cPH8+F4Kz+BYTSMWTZtPLQ== X-Received: by 2002:a5d:4c4e:: with SMTP id n14mr9845340wrt.260.1573226817077; Fri, 08 Nov 2019 07:26:57 -0800 (PST) Received: from localhost.localdomain ([85.195.192.192]) by smtp.gmail.com with ESMTPSA id w18sm6579232wrp.31.2019.11.08.07.26.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2019 07:26:56 -0800 (PST) From: Jean-Philippe Brucker To: iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, guohanjun@huawei.com, sudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org, will@kernel.org, robin.murphy@arm.com, zhangfei.gao@linaro.org, eric.auger@redhat.com, jonathan.cameron@huawei.com Subject: [PATCH v2 8/8] iommu/arm-smmu-v3: Add support for PCI PASID Date: Fri, 8 Nov 2019 16:25:08 +0100 Message-Id: <20191108152508.4039168-9-jean-philippe@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191108152508.4039168-1-jean-philippe@linaro.org> References: <20191108152508.4039168-1-jean-philippe@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable PASID for PCI devices that support it. Since the SSID tables are allocated by arm_smmu_attach_dev(), PASID has to be enabled early enough. arm_smmu_dev_feature_enable() would be too late, since by that time the main DMA domain has already been attached. Do it in add_device() instead. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 51 ++++++++++++++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) -- 2.23.0 Reviewed-by: Jonathan Cameron diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 88ec0bf33492..3ee313c08325 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -2633,6 +2633,49 @@ static void arm_smmu_disable_ats(struct arm_smmu_master *master) atomic_dec(&smmu_domain->nr_ats_masters); } +static int arm_smmu_enable_pasid(struct arm_smmu_master *master) +{ + int ret; + int features; + int num_pasids; + struct pci_dev *pdev; + + if (!dev_is_pci(master->dev)) + return -ENOSYS; + + pdev = to_pci_dev(master->dev); + + features = pci_pasid_features(pdev); + if (features < 0) + return -ENOSYS; + + num_pasids = pci_max_pasids(pdev); + if (num_pasids <= 0) + return -ENOSYS; + + ret = pci_enable_pasid(pdev, features); + if (!ret) + master->ssid_bits = min_t(u8, ilog2(num_pasids), + master->smmu->ssid_bits); + return ret; +} + +static void arm_smmu_disable_pasid(struct arm_smmu_master *master) +{ + struct pci_dev *pdev; + + if (!dev_is_pci(master->dev)) + return; + + pdev = to_pci_dev(master->dev); + + if (!pdev->pasid_enabled) + return; + + master->ssid_bits = 0; + pci_disable_pasid(pdev); +} + static void arm_smmu_detach_dev(struct arm_smmu_master *master) { unsigned long flags; @@ -2841,13 +2884,16 @@ static int arm_smmu_add_device(struct device *dev) master->ssid_bits = min(smmu->ssid_bits, fwspec->num_pasid_bits); + /* Note that PASID must be enabled before, and disabled after ATS */ + arm_smmu_enable_pasid(master); + if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB)) master->ssid_bits = min_t(u8, master->ssid_bits, CTXDESC_LINEAR_CDMAX); ret = iommu_device_link(&smmu->iommu, dev); if (ret) - goto err_free_master; + goto err_disable_pasid; group = iommu_group_get_for_dev(dev); if (IS_ERR(group)) { @@ -2860,6 +2906,8 @@ static int arm_smmu_add_device(struct device *dev) err_unlink: iommu_device_unlink(&smmu->iommu, dev); +err_disable_pasid: + arm_smmu_disable_pasid(master); err_free_master: kfree(master); fwspec->iommu_priv = NULL; @@ -2880,6 +2928,7 @@ static void arm_smmu_remove_device(struct device *dev) arm_smmu_detach_dev(master); iommu_group_remove_device(dev); iommu_device_unlink(&smmu->iommu, dev); + arm_smmu_disable_pasid(master); kfree(master); iommu_fwspec_free(dev); }