From patchwork Tue Oct 1 06:16:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 174810 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp8116065ill; Mon, 30 Sep 2019 23:16:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqxfz1a4VlDwbOSFzRNztyWeGDUv027EAO7/DCPewCRaUbRzqEEd6+tmr5LljHPhhJX4xRsi X-Received: by 2002:a17:906:c282:: with SMTP id r2mr21377543ejz.207.1569910610225; Mon, 30 Sep 2019 23:16:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569910610; cv=none; d=google.com; s=arc-20160816; b=s1DhmUyX+/BWP30jYAoOelK3zcnB3GMO7o8P1efsnll2Z/jwm1kl8ojlpLuv4lDwls 7iqpi7pP5p+mTeZ5rCgP7os5FwChTqbekgU59yKUmPWV03nB8oHVfnuiPBmwcv4Q4w7b FC4oMF8HRX8sDsqYWbDwNQYyqYFFceAyejeEfjVSeNLlRtD4OQCnGgbbArAr2glUN5+1 DW2Lu8rdio90z6yUxZIoJZPVPPoQr+NPNMpF6p4tvsnELygO7JoaFCf2qkJnb/I3Lc8j 9f1beCoxhdbovsXLD7tEY4xwjoKx0dMS6l1D24waifFLFjFoHV8IhY0iRK4sTxSAEGDT lo8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DfFRpw7GPtmxTaDqZ1grWeRPjfw/85ryCRcZj2Zxl7w=; b=xppW/g75na9txKFxVyluTeC6zmPPBBjnuiGjxjGbSyiRsxm652vP5Oadnmwsj+1Opl GGX6IW4PyJw732rHoPEEDFGCdXix0zGk2D1VDlK5Z+geeXXBwiD1Ycjalh7IqoIgB0JS qV1/0q1np0A0+72XLgh74gbfDuPP4FMY3rWMxYQEzFhyTUuXK1Zdvh0sVxNtgLzjp/UY D0PsdehFuXG7e8GWPWxiTYRZN5UbpBhb1t9muxMzZnZdrMLHGFa8PtZVDnWLfdJks4DF xXpeuGPPt/ynTmUME8PzMTbyLMDWVTumzZurHcWiFV2QMqv4+ugpB4ahkVqkdg5TckcG 8PMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=SUVLZ090; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a3si8272090edr.20.2019.09.30.23.16.50; Mon, 30 Sep 2019 23:16:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=SUVLZ090; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731822AbfJAGQq (ORCPT + 8 others); Tue, 1 Oct 2019 02:16:46 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:42290 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726822AbfJAGQq (ORCPT ); Tue, 1 Oct 2019 02:16:46 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x916GOfC019950; Tue, 1 Oct 2019 01:16:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569910584; bh=DfFRpw7GPtmxTaDqZ1grWeRPjfw/85ryCRcZj2Zxl7w=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=SUVLZ090zdsM++Tt33bRyE+gEPU9SZeT11VxMNetT+P7mwlBJ2zf2IkAHF7Lq7wvX fMhTkrxqLicwAHBlULDU1+/QSSMST9erARQvpBRefTwGLK4Jm5iXcwBo/9x9KKFuVq +YMfzYhMhuXZNIacP8ecS8zfTu5hL7leufS3TqHk= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x916GOiL017863 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 1 Oct 2019 01:16:24 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 1 Oct 2019 01:16:23 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 1 Oct 2019 01:16:13 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x916GGX6090310; Tue, 1 Oct 2019 01:16:20 -0500 From: Peter Ujfalusi To: , , , CC: , , , , , , , , , Subject: [PATCH v3 01/14] bindings: soc: ti: add documentation for k3 ringacc Date: Tue, 1 Oct 2019 09:16:51 +0300 Message-ID: <20191001061704.2399-2-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191001061704.2399-1-peter.ujfalusi@ti.com> References: <20191001061704.2399-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Grygorii Strashko The Ring Accelerator (RINGACC or RA) provides hardware acceleration to enable straightforward passing of work between a producer and a consumer. There is one RINGACC module per NAVSS on TI AM65x and j721e. This patch introduces RINGACC device tree bindings. Signed-off-by: Grygorii Strashko Signed-off-by: Peter Ujfalusi Reviewed-by: Rob Herring --- .../devicetree/bindings/soc/ti/k3-ringacc.txt | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt new file mode 100644 index 000000000000..86954cf4fa99 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt @@ -0,0 +1,59 @@ +* Texas Instruments K3 NavigatorSS Ring Accelerator + +The Ring Accelerator (RA) is a machine which converts read/write accesses +from/to a constant address into corresponding read/write accesses from/to a +circular data structure in memory. The RA eliminates the need for each DMA +controller which needs to access ring elements from having to know the current +state of the ring (base address, current offset). The DMA controller +performs a read or write access to a specific address range (which maps to the +source interface on the RA) and the RA replaces the address for the transaction +with a new address which corresponds to the head or tail element of the ring +(head for reads, tail for writes). + +The Ring Accelerator is a hardware module that is responsible for accelerating +management of the packet queues. The K3 SoCs can have more than one RA instances + +Required properties: +- compatible : Must be "ti,am654-navss-ringacc"; +- reg : Should contain register location and length of the following + named register regions. +- reg-names : should be + "rt" - The RA Ring Real-time Control/Status Registers + "fifos" - The RA Queues Registers + "proxy_gcfg" - The RA Proxy Global Config Registers + "proxy_target" - The RA Proxy Datapath Registers +- ti,num-rings : Number of rings supported by RA +- ti,sci-rm-range-gp-rings : TI-SCI RM subtype for GP ring range +- ti,sci : phandle on TI-SCI compatible System controller node +- ti,sci-dev-id : TI-SCI device id +- msi-parent : phandle for "ti,sci-inta" interrupt controller + +Optional properties: + -- ti,dma-ring-reset-quirk : enable ringacc / udma ring state interoperability + issue software w/a + +Example: + +ringacc: ringacc@3c000000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x3c000000 0x0 0x400000>, + <0x0 0x38000000 0x0 0x400000>, + <0x0 0x31120000 0x0 0x100>, + <0x0 0x33000000 0x0 0x40000>; + reg-names = "rt", "fifos", + "proxy_gcfg", "proxy_target"; + ti,num-rings = <818>; + ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ + ti,dma-ring-reset-quirk; + ti,sci = <&dmsc>; + ti,sci-dev-id = <187>; + msi-parent = <&inta_main_udmass>; +}; + +client: + +dma_ipx: dma_ipx@ { + ... + ti,ringacc = <&ringacc>; + ... +}