From patchwork Wed Aug 28 07:19:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 172333 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp364911ily; Wed, 28 Aug 2019 00:20:10 -0700 (PDT) X-Google-Smtp-Source: APXvYqw0XxXEv4srRKKPY5SinH3enPdtI39S98592PBAtwwB497D7IrvMyuJuhs1mr2dJ6o7nA2K X-Received: by 2002:a65:528d:: with SMTP id y13mr2298511pgp.120.1566976810059; Wed, 28 Aug 2019 00:20:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566976810; cv=none; d=google.com; s=arc-20160816; b=YnJgwavo3vHwbdeZN87uZjsPRWf3Mc0RSv/PydVs5fPgwO2KkPRF3sbVFD2P3Z0sDa 2ppZeg5TN4q1HXDoeoo/XxumXptwc6JERA9I61chNUU5vI4eeE4ZXqGbjjXRkBv+1Quk 4cvhAYcLbhhQCDzaWoCBOUSYjvnv/ImWhw2Od+5zMzzjY2xU6OQ7Aqnb/mpdCmNsQLSx QP6L/QiarF/GOdhWlv/eIAEasvLkK+G5j59uzB3MG4ifr4Iodlnp6UkZ5nWX3lMXRalZ 65qFX67kjvSH+9z9abCpNU1HG9xYM+oZgHd9AUpiKMkeLkJFqAlecYX7pNZYCTu5flyc 5SDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=MaJKqEmPi2ARgN2dmtUrxd+FuRc6LkB83YP9HuVdTr8=; b=VhTVEmef+ePfLfOkGYquuP6XK5WfquiGEMiiRCIf9N4s9o0h9debG7EznXw+mI5AXa WqEaOAzN/sHEz7ZEEGwboA9Sa6UHFmdkep3tVgXe5jFlfhFrtRfWPaGjIcZ70I5io+6I /OHhH0/jfog1kb1MMEhfN5iFQ6x5LmQrGCvbj7QVbi5X/qhVFXLWNLrRG+MBzuI4cxl0 DyzuTspYku5fhELuPC4tzJGuW6dKmHe9Kmt3g23Ux+zRJI9FvuwA3vw603ZRcmCkEojN ODyjAehDXhnDNw7JCIFnRZC/6AJgrCYRGdEQIY9Ut9bQw/UE+0+oOmbOBjHyMdcNu7OV S18w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TKgJcyum; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f9si1222986plo.306.2019.08.28.00.20.09; Wed, 28 Aug 2019 00:20:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TKgJcyum; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726341AbfH1HUI (ORCPT + 8 others); Wed, 28 Aug 2019 03:20:08 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:52982 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726252AbfH1HUI (ORCPT ); Wed, 28 Aug 2019 03:20:08 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7Jxwa112292; Wed, 28 Aug 2019 02:19:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566976799; bh=MaJKqEmPi2ARgN2dmtUrxd+FuRc6LkB83YP9HuVdTr8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TKgJcyumN+Uh48ci5bfK/qWgiynhCaRHxNXvrefoTDyGRNN4Bp01ddpml62kxyZFt 6ycXiTl9BSFNjZSdAHx/W/o6kAYn7EkAFJdrOp9zbUfgNbxqIK83qWT2cO+O7KLeM0 D7+sn99CefCR7PoeW19GC2oD6bOz8zfvSBNpqHDY= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7Jxoe082890 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:19:59 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:19:59 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:19:59 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JmfG052201; Wed, 28 Aug 2019 02:19:57 -0500 From: Tero Kristo To: , , , , CC: , , Subject: [PATCHv2 04/11] soc: ti: omap-prm: add support for denying idle for reset clockdomain Date: Wed, 28 Aug 2019 10:19:34 +0300 Message-ID: <20190828071941.32378-5-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828071941.32378-1-t-kristo@ti.com> References: <20190828071941.32378-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org TI SoCs hardware reset signals require the parent clockdomain to be in force wakeup mode while de-asserting the reset, otherwise it may never complete. To support this, add pdata hooks to control the clockdomain directly. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 34 +++++++++++++++++++++++++--- include/linux/platform_data/ti-prm.h | 21 +++++++++++++++++ 2 files changed, 52 insertions(+), 3 deletions(-) create mode 100644 include/linux/platform_data/ti-prm.h -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index afeb70761b27..38998ce19c71 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -16,6 +16,8 @@ #include #include +#include + struct omap_rst_map { s8 rst; s8 st; @@ -24,6 +26,7 @@ struct omap_rst_map { struct omap_prm_data { u32 base; const char *name; + const char *clkdm_name; u16 rstctrl; u16 rstst; const struct omap_rst_map *rstmap; @@ -38,6 +41,8 @@ struct omap_prm { struct omap_reset_data { struct reset_controller_dev rcdev; struct omap_prm *prm; + struct clockdomain *clkdm; + struct device *dev; }; #define to_omap_reset_data(p) container_of((p), struct omap_reset_data, rcdev) @@ -128,6 +133,8 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, int st_bit; bool has_rstst; int timeout = 0; + struct ti_prm_platform_data *pdata = dev_get_platdata(reset->dev); + int ret = 0; if (!_is_valid_reset(reset, id)) return -EINVAL; @@ -149,13 +156,15 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, writel_relaxed(v, reset->prm->base + reset->prm->data->rstst); } + pdata->clkdm_deny_idle(reset->clkdm); + /* de-assert the reset control line */ v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); v &= ~(1 << id); writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); if (!has_rstst) - return 0; + goto exit; /* wait for the status to be set */ while (1) { @@ -167,13 +176,17 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, if (timeout > OMAP_RESET_MAX_WAIT) { pr_err("%s: timedout waiting for %s:%lu\n", __func__, dev_name(rcdev->dev), id); - return -EBUSY; + ret = -EBUSY; + goto exit; } udelay(1); } - return 0; +exit: + pdata->clkdm_allow_idle(reset->clkdm); + + return ret; } static const struct reset_control_ops omap_reset_ops = { @@ -186,6 +199,8 @@ static int omap_prm_reset_init(struct platform_device *pdev, struct omap_prm *prm) { struct omap_reset_data *reset; + struct ti_prm_platform_data *pdata = dev_get_platdata(&pdev->dev); + char buf[32]; /* * Check if we have controllable resets. If either rstctrl is non-zero @@ -195,6 +210,11 @@ static int omap_prm_reset_init(struct platform_device *pdev, if (!prm->data->rstctrl && !(prm->data->flags & OMAP_PRM_HAS_RSTCTRL)) return 0; + /* Check if we have the pdata callbacks in place */ + if (!pdata->clkdm_lookup || !pdata->clkdm_deny_idle || + !pdata->clkdm_allow_idle) + return -EINVAL; + reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); if (!reset) return -ENOMEM; @@ -203,9 +223,17 @@ static int omap_prm_reset_init(struct platform_device *pdev, reset->rcdev.ops = &omap_reset_ops; reset->rcdev.of_node = pdev->dev.of_node; reset->rcdev.nr_resets = OMAP_MAX_RESETS; + reset->dev = &pdev->dev; reset->prm = prm; + sprintf(buf, "%s_clkdm", prm->data->clkdm_name ? prm->data->clkdm_name : + prm->data->name); + + reset->clkdm = pdata->clkdm_lookup(buf); + if (!reset->clkdm) + return -EINVAL; + return devm_reset_controller_register(&pdev->dev, &reset->rcdev); } diff --git a/include/linux/platform_data/ti-prm.h b/include/linux/platform_data/ti-prm.h new file mode 100644 index 000000000000..28154c3226c2 --- /dev/null +++ b/include/linux/platform_data/ti-prm.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * TI PRM (Power & Reset Manager) platform data + * + * Copyright (C) 2019 Texas Instruments, Inc. + * + * Tero Kristo + */ + +#ifndef _LINUX_PLATFORM_DATA_TI_PRM_H +#define _LINUX_PLATFORM_DATA_TI_PRM_H + +struct clockdomain; + +struct ti_prm_platform_data { + void (*clkdm_deny_idle)(struct clockdomain *clkdm); + void (*clkdm_allow_idle)(struct clockdomain *clkdm); + struct clockdomain * (*clkdm_lookup)(const char *name); +}; + +#endif /* _LINUX_PLATFORM_DATA_TI_PRM_H */