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[209.132.180.67]) by mx.google.com with ESMTP id t22si252398pja.12.2019.08.22.10.34.17; Thu, 22 Aug 2019 10:34:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gv0f9HSo; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389964AbfHVRdk (ORCPT + 8 others); Thu, 22 Aug 2019 13:33:40 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:43179 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2404415AbfHVRZZ (ORCPT ); Thu, 22 Aug 2019 13:25:25 -0400 Received: by mail-pl1-f194.google.com with SMTP id 4so3828669pld.10 for ; Thu, 22 Aug 2019 10:25:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kgB5pCuOS2QWyyNQUlCeMbbF7mRF+VE6sHHJ2GG7b1c=; b=gv0f9HSogQdG7i5xlGVbdaMiJq65fe44ST/fS08V+vh3ZHU48LmMKQGJ3ZT3ObS4MZ sUXBKHJlyeqGOnIkvLoaR38ZDwDbGeN0gvd7WSEurkxWl3T4S6jJX3AwyVaKm9GlpRT0 mkZn+cpwiRuRGdNRDTwaQ7pdmFlu9vCGBcb4vx8eF7vhndslapZsDupegiEwKWC8jfRn jO93tPu7TUjSNfpkOLbrqrijqKj6OF64AfUsPskbAkSmBILVVcpIj9bD0uT9QHf6crDF R7UQGd2RcpHooncpyEBxVoZHq4zLw7AyeZT6QOMq4Atn01BlWXvXAlrIU7laeYp9vkXW hsyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kgB5pCuOS2QWyyNQUlCeMbbF7mRF+VE6sHHJ2GG7b1c=; b=E7/qQ2GgtuWzwiOrTKz2oAS8W27zVzc8OHFiAHwTTnBboC8G6mJ0cD3kDVLpkb9f8p jYPMjZypEN3h+DQh3Usz+QCTFTbxzi2OsVETvufzgZXwYp2Op2SoxPdz6cixdnXM+G6i U3m2XdQ8gzf69SqgClnrqDIlw+uV0dnas/mlngRcLwBMqRq9gjOPW3IJlIMXtO8vHhbP IhLOrWtt5MSvzfJ+d1AIzfDw8WFLCj+e4RnxHTfdq12K4mNzMPeHCHuVah9gw9pVLAvl PGvknoVS7Y54YSLMKvwoo4uwk3fnib8biN4+i+bXVu/C/I1QXdJxzsV1b8K4G6z2eXus 8/kg== X-Gm-Message-State: APjAAAVCZNyLuM5Ddxyi468YEIrHjoQ4SomULWu5e5/mVRAaVFYJc0Wm 7nuKa6UyVkS9Z5tJ6AOSgvLg X-Received: by 2002:a17:902:a706:: with SMTP id w6mr42326828plq.166.1566494724395; Thu, 22 Aug 2019 10:25:24 -0700 (PDT) Received: from localhost.localdomain ([2405:204:71cc:5738:24ad:193e:4b59:8a76]) by smtp.gmail.com with ESMTPSA id r12sm31705798pgb.73.2019.08.22.10.25.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2019 10:25:23 -0700 (PDT) From: Manivannan Sadhasivam To: sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, fisher.cheng@bitmain.com, alec.lin@bitmain.com, Manivannan Sadhasivam Subject: [PATCH v4 6/8] arm64: dts: bitmain: Source common clock for UART controllers Date: Thu, 22 Aug 2019 22:54:24 +0530 Message-Id: <20190822172426.25879-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190822172426.25879-1-manivannan.sadhasivam@linaro.org> References: <20190822172426.25879-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Remove fixed clock and source common clock for UART controllers. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts | 9 --------- arch/arm64/boot/dts/bitmain/bm1880.dtsi | 12 ++++++++++++ 2 files changed, 12 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts index 3e8c70778e24..7a2c7f9c2660 100644 --- a/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts +++ b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts @@ -49,12 +49,6 @@ reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB }; - uart_clk: uart-clk { - compatible = "fixed-clock"; - clock-frequency = <500000000>; - #clock-cells = <0>; - }; - soc { gpio0: gpio@50027000 { porta: gpio-controller@0 { @@ -173,21 +167,18 @@ &uart0 { status = "okay"; - clocks = <&uart_clk>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { status = "okay"; - clocks = <&uart_clk>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &uart2 { status = "okay"; - clocks = <&uart_clk>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2_default>; }; diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi index 8471662413da..fa6e6905f588 100644 --- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi +++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi @@ -174,6 +174,9 @@ uart0: serial@58018000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x58018000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-shift = <2>; reg-io-width = <4>; @@ -184,6 +187,9 @@ uart1: serial@5801A000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x5801a000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-shift = <2>; reg-io-width = <4>; @@ -194,6 +200,9 @@ uart2: serial@5801C000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x5801c000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-shift = <2>; reg-io-width = <4>; @@ -204,6 +213,9 @@ uart3: serial@5801E000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x5801e000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-shift = <2>; reg-io-width = <4>;