From patchwork Wed Aug 21 18:42:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 171982 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp1347223ily; Wed, 21 Aug 2019 11:44:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqz3hdwJM6SpyPB7K2n62QI2lnBq9/TPEo4U3ygrAHWRwHTQAqci12yPc1pjyerxfLG53gzu X-Received: by 2002:a62:b408:: with SMTP id h8mr36269042pfn.46.1566413052958; Wed, 21 Aug 2019 11:44:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566413052; cv=none; d=google.com; s=arc-20160816; b=yfi3AKD/Q1sGjtx3rTbSNgCZrol7+7V49OFz65I19lMuv7l5t1lI8f+dX826U6JlI8 AORmeYzcUSsVXmkYP3Thd3DW0+7NugmN3QHsQHcP1Mjqw2q//xPLbRNETxd/xRfPH/nb kouB3pKmUjv6ezbuabJIgiPQmQ2SkblVSsN9tXCWaBruCvKzAd08P6rpujampS3XYoGR 4HnAt3xdLZhP+y16F1hgiry9A1EZd42g6M4eX2/WfAQJUt95fQI8eDa86QcWnsEHPCvK GVS7v3df8RvpnRDjFG76LsAItqMx8mf1SJyUw0z3a8Z5dXIwJsbQEt7hIenRYIV9SUkP v4mw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=BDOBjBfSxBPjtK9qF44Pg0m+Gp8s0Bb34A2KVpYKeYA=; b=vKZP7xv55Tnyui14NLQVdDvJg4KuRlSYygBLHB5EFImTE0B0IoCefws99vOVzQoh7c 5px2q9W8r5yUu6zPd+BsC+zADB3+CfQszIL/Kl8t+cfC/uZ/ZXH/1Ljh9aXf8o6rzom9 reG01/TNlTGqMZWHrqKtQI0jNPhVAeuHEu4JIT2cpUFfDieOcye0qssGkF+cszP7t4oz 86DwX7jRhQZcudcedfzGSo8I0OBzG7fXkW1tJrr2+tHgQeR2FVvPB3PrVjdxGqN0toqS VKuYpG/7B0iI9NgOBVaIJfuCedaDtXAauwaD+5Cm7sS1IRH+DuxFTqZQnlKG6OrYwWw+ HCwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=XYBfCGN9; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c1si16328006pfo.68.2019.08.21.11.44.12; Wed, 21 Aug 2019 11:44:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=XYBfCGN9; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728511AbfHUSoM (ORCPT + 8 others); Wed, 21 Aug 2019 14:44:12 -0400 Received: from mail.kernel.org ([198.145.29.99]:39836 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728653AbfHUSoK (ORCPT ); Wed, 21 Aug 2019 14:44:10 -0400 Received: from localhost.localdomain (unknown [106.201.100.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0DCC422DD3; Wed, 21 Aug 2019 18:44:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1566413048; bh=Dp1E0NU05STvIhret+1ooR57CeQpbfSceCtIkzTi/6c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XYBfCGN9XEBnOvZPQXM3phAqaAxRnMg022ZSpsmvzceNu5YI2ETfHG0zcqpm2RFSV 7Lg0v809I2CfG7szynDwsCAJ9+940i0lSUVCKmgDIkUY49RgjwpJmmq7z+6qv1k9t8 Ti/Ub0chhO2ytVkbbY1eK8wK7Id4N/XSESogJXlE= From: Vinod Koul To: Andy Gross Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Rob Herring , Mark Rutland , Stephen Boyd , Sibi Sankar , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Niklas Cassel Subject: [PATCH v4 1/8] arm64: dts: qcom: sm8150: Add base dts file Date: Thu, 22 Aug 2019 00:12:32 +0530 Message-Id: <20190821184239.12364-2-vkoul@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190821184239.12364-1-vkoul@kernel.org> References: <20190821184239.12364-1-vkoul@kernel.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This add base DTS file with cpu, psci, firmware, clock node tlmm and spmi and enables boot to console Signed-off-by: Vinod Koul Reviewed-by: Niklas Cassel --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 308 +++++++++++++++++++++++++++ 1 file changed, 308 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8150.dtsi -- 2.20.1 Reviewed-by: Amit Kucheria diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi new file mode 100644 index 000000000000..417b21d1897c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019, Linaro Limited + */ + +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; + clock-output-names = "sleep_clk"; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm8150", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sm8150"; + reg = <0x0 0x00100000 0x0 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "bi_tcxo", + "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc 123>, + <&gcc 124>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart2: serial@a90000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00a90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc 105>; + interrupts = ; + status = "disabled"; + }; + }; + + tlmm: pinctrl@3100000 { + compatible = "qcom,sm8150-pinctrl"; + reg = <0x0 0x03100000 0x0 0x300000>, + <0x0 0x03500000 0x0 0x300000>, + <0x0 0x03900000 0x0 0x300000>, + <0x0 0x03D00000 0x0 0x300000>; + reg-names = "west", "east", "north", "south"; + interrupts = ; + gpio-ranges = <&tlmm 0 0 175>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c440000 0x0 0x0001100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x0100000>, + <0x0 0x0e700000 0x0 0x00a0000>, + <0x0 0x0c40a000 0x0 0x0026000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + timer@17c20000 { + #address-cells = <2>; + #size-cells = <2>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17c20000 0x0 0x1000>; + clock-frequency = <19200000>; + + frame@17c21000{ + frame-number = <0>; + interrupts = , + ; + reg = <0x0 0x17c21000 0x0 0x1000>, + <0x0 0x17c22000 0x0 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = ; + reg = <0x0 0x17c23000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = ; + reg = <0x0 0x17c25000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = ; + reg = <0x0 0x17c26000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = ; + reg = <0x0 0x17c29000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = ; + reg = <0x0 0x17c2b000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = ; + reg = <0x0 0x17c2d000 0x0 0x1000>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +};