From patchwork Thu Jul 25 00:10:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 169655 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp10886783ilk; Wed, 24 Jul 2019 17:10:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqw5Q+NMb908NN9yVXnKdzcc/L7rt5Oiq8KG5XSolhrZ7A+EHY1ROTUqP/SPKONE+RyRxm2o X-Received: by 2002:a17:90a:ad86:: with SMTP id s6mr90467645pjq.42.1564013435266; Wed, 24 Jul 2019 17:10:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564013435; cv=none; d=google.com; s=arc-20160816; b=CzoDpeLDeRMMFNbjQdyRks+VKoF428Q/nryrqVofybr6AavZBrwSlWI9re7srflZIw orONsCJ67RiNcUltmg7lmMDKbVsUobNpBwHS+1xPmIJdtqC+HzM4i1Uf9ow4pbFJ3yJp qgWShpYOfP/1j+MdsyzmJClSbS56zl5SX05Bw4xTb/G9NNVauva7+19Y1QtuOevPH3AM DzdjOaybSouNd4Qo9VcO1JPz3ylRspvqExTyi/eZH/rB/HNL6QCxFu4ClfWbYtNJtsB2 pQh8+J8MYDIG5dUjUgWrd4gjORFLxqZ1JzUB+GNEIdoXrr7aiD/JCBIdjYpnAeFgOGQD JRzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=r6VFLcRsIVD2QJoHeMzGmZVijy4Xhtp+jaJARX48jrs=; b=qpnhBnquN6zwUUYnQ7mFLiGlclHFcP/vPYzETkNe0XTFbLwmYrh9a9UfYUOhYQDl0J LR5YtuL/QBdBtnj8a0eN6832C/X8B2rMZLhNKq0PoQzpxe0Bb9g15C13FdrXf4VssMSq gjvdj0Oi3k1ttk9S1TC6Vb2p1WNq7Hr4+03f65rl3MtcvAwDMq7ZQY0Kj4vyVd9hXOIu P4t8btymTGzdgyrnXZkrKMNcOKi5IovDPYi5mgzleCJw2fy5swQwg1/4yjUUUEZH0ybb g8mr7d2bCKXTa+d/wiFZhQv7wp5Ki3qcPRFRKNiAknptHUmU7Iivk/OdHPoWjwimJt7L pBcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=pwlCvcTK; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w6si16163393pjr.100.2019.07.24.17.10.35; Wed, 24 Jul 2019 17:10:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=pwlCvcTK; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388601AbfGYAKe (ORCPT + 8 others); Wed, 24 Jul 2019 20:10:34 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:49506 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388569AbfGYAKe (ORCPT ); Wed, 24 Jul 2019 20:10:34 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x6P0AVjI015380; Wed, 24 Jul 2019 19:10:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1564013431; bh=r6VFLcRsIVD2QJoHeMzGmZVijy4Xhtp+jaJARX48jrs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pwlCvcTKa9n29g16AhqMmhEgz+VH1MCJst9MTeYm9rwYXXqUqPHTiHUjmHYVqVC8R TJXCd8kDDK6lEpp5Uvfosh2sZ8ywZmmm/12Wsex47gDukrj92JcexDZ62h+zy4DQWW G0p7HpUN2u2vmysV7QVHuTU+Q5KlzcLeGZDkZJVk= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x6P0AVVF026501 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 24 Jul 2019 19:10:31 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 24 Jul 2019 19:10:31 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 24 Jul 2019 19:10:31 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x6P0AVil108012; Wed, 24 Jul 2019 19:10:31 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x6P0AVZ03284; Wed, 24 Jul 2019 19:10:31 -0500 (CDT) From: Suman Anna To: Tero Kristo , Nishanth Menon CC: , , Suman Anna Subject: [PATCH v2 4/4] arm64: dts: ti: k3-j721e-common-proc-board: Add IPC sub-mailbox nodes Date: Wed, 24 Jul 2019 19:10:20 -0500 Message-ID: <20190725001020.23781-5-s-anna@ti.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190725001020.23781-1-s-anna@ti.com> References: <20190725001020.23781-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the sub-mailbox nodes that are used to communicate between MPU and various remote processors present in the J721E SoCs to the J721E common processor board. These include the R5F remote processors in the dual-R5F cluster (MCU_R5FSS0) in the MCU domain and the two dual-R5F clusters (MAIN_R5FSS0 & MAIN_R5FSS1) in the MAIN domain; the two C66x DSP remote processors and the single C71x DSP remote processor in the MAIN domain. These sub-mailbox nodes utilize the System Mailbox clusters 0 through 4. All the remaining mailbox clusters are currently not used on A72 core, and so are disabled. The sub-mailbox nodes added match the hard-coded mailbox configuration used within the TI RTOS IPC software packages. The R5F processor sub-systems are assumed to be running in Split mode, so a sub-mailbox node is used by each of the R5F cores. Only the sub-mailbox node for the first R5F core in each cluster is used in case of a Lockstep mode for that R5F cluster. NOTE: The GIC_SPI interrupts to be used are dynamically allocated and managed by the System Firmware through the ti-sci-intr irqchip driver. So, only valid interrupts (each cluster's User 0 IRQ output) that are used by the sub-mailbox devices are enabled. This is done to minimize the number of NavSS Interrupt Router outputs utilized. Signed-off-by: Suman Anna --- v2: - Sub-mailboxes added in board dts file instead of base dtsi file - Unused mailbox clusters 5 through 11 disabled - Patch description and title updated v1: https://patchwork.kernel.org/patch/11053409/ .../dts/ti/k3-j721e-common-proc-board.dts | 93 +++++++++++++++++++ 1 file changed, 93 insertions(+) -- 2.22.0 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index c680123f067c..93ae1d49dcc1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -48,3 +48,96 @@ /* UART not brought out */ status = "disabled"; }; + +&mailbox0_cluster0 { + interrupts = <214 0>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + interrupts = <215 0>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + interrupts = <216 0>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + interrupts = <217 0>; + + mbox_c66_0: mbox-c66-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c66_1: mbox-c66-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + interrupts = <218 0>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster5 { + status = "disabled"; +}; + +&mailbox0_cluster6 { + status = "disabled"; +}; + +&mailbox0_cluster7 { + status = "disabled"; +}; + +&mailbox0_cluster8 { + status = "disabled"; +}; + +&mailbox0_cluster9 { + status = "disabled"; +}; + +&mailbox0_cluster10 { + status = "disabled"; +}; + +&mailbox0_cluster11 { + status = "disabled"; +};