From patchwork Fri Jul 5 15:12:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 168547 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp3701439ilk; Fri, 5 Jul 2019 08:13:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqy76qeAHvNRBdVjL72IF5cguYqVGXKTLHxs/Ut6Adp/phHd08pqFJsmF1NoXhXONLJfFw9b X-Received: by 2002:a17:902:1125:: with SMTP id d34mr6282006pla.40.1562339592219; Fri, 05 Jul 2019 08:13:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562339592; cv=none; d=google.com; s=arc-20160816; b=ycevNGixM9mS2vobCfZr9LSnfWlwN8GkXnRt+FFciuwk/H7eVPxSDnk27mZGJ9AhcN 42qeS44XDvziS5AL6LXKNh7xyYme7T5w9dlUiD95HngIXQxWLf6rK9DXKnwQ5ZwLVyBx r0TvCDBn1O+9Ee0tjAG60YjRvQWAIfgRvzu/fQgTVIvVlpPWt2ofyw8Vof7NnvUhs6mZ iCzkC8eOAR4zCKJNIZAQx3INukmSUUgTg67T0xQFdfE5hnZCJ/a9JdXi4p0eWGASaxI1 RvQazFwk0C8inykYEJOn1DId0bXWuf3faM0u6jiDOYC17b20Y0jjb3TSrM252i6bNRjW DK7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=R9/ML2By2Vb9VJ9ig9TmuZ+7bbZ0eArmGw/7g8VKZyU=; b=bzNotAdVhHuAU477+0ebBEo/S7k8YxQ7XzXORfD8yR8IILHYBC0abNeJOxzVB1CeB5 A9N55Q3KTRDOg5AxwpZ3Ai0GPboFsL6cz/RFNaJ912hkLKe51X/apPvTQqlhIH2myWrK iu4mo/9sMtwJzwznCFDN/5e5YA+ecuKOd3S/wQ3NKrxjqdyrbHM18XyXd+4hJmls3otK y9MgVl/lqzaJ6ctRAAgRpoGmAm+0H0JZopHB5deCEdkbGMd67+K4AFqbEl8WztnsdnfF 0U0p7xaIJmIgebdBUUKpHsBE3qA1nQJWEjdKdpmnZ9KqXdTLG7hDQ0ASzu4AcXbx5hgi gGhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FW1rubOe; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p17si8966524plo.310.2019.07.05.08.13.12; Fri, 05 Jul 2019 08:13:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FW1rubOe; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727811AbfGEPNL (ORCPT + 8 others); Fri, 5 Jul 2019 11:13:11 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:51172 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727717AbfGEPNL (ORCPT ); Fri, 5 Jul 2019 11:13:11 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x65FD7gI112774; Fri, 5 Jul 2019 10:13:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1562339587; bh=R9/ML2By2Vb9VJ9ig9TmuZ+7bbZ0eArmGw/7g8VKZyU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FW1rubOekYEudYR25THRGs25j+KTtaOZJUEMd3kNJqpKS9uVSLA59Fuqta4Yc7/SX +VCRwHaHxNau3FSg+wmF6+RMsPTRad1mBZ6FQj1ZzT2C6v8mTYuzbvcfmUdZB0EH+h dW72Kv8Z5WCJgzlf7rR+zMKoCZB+DXoB07AGb7Mk= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x65FD78D012366 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 5 Jul 2019 10:13:07 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 5 Jul 2019 10:13:07 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 5 Jul 2019 10:13:07 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x65FD64p111909; Fri, 5 Jul 2019 10:13:07 -0500 From: Grygorii Strashko To: Santosh Shilimkar CC: Sekhar Nori , Murali Karicheri , , , , Grygorii Strashko Subject: [RESEND PATCH next v2 2/6] ARM: dts: k2e-clocks: add input ext. fixed clocks tsipclka/b Date: Fri, 5 Jul 2019 18:12:43 +0300 Message-ID: <20190705151247.30422-3-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190705151247.30422-1-grygorii.strashko@ti.com> References: <20190705151247.30422-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add set of fixed, external input clocks definitions for TSIPCLKA, TSIPCLKB clocks. Such clocks can be used as reference clocks for some HW modules (as cpts, for example) by configuring corresponding clock muxes. For these clocks real frequencies have to be defined in board files. Signed-off-by: Grygorii Strashko --- arch/arm/boot/dts/keystone-k2e-clocks.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.17.1 diff --git a/arch/arm/boot/dts/keystone-k2e-clocks.dtsi b/arch/arm/boot/dts/keystone-k2e-clocks.dtsi index f7592155a740..cf30e007fea3 100644 --- a/arch/arm/boot/dts/keystone-k2e-clocks.dtsi +++ b/arch/arm/boot/dts/keystone-k2e-clocks.dtsi @@ -71,4 +71,24 @@ clocks { reg-names = "control", "domain"; domain-id = <29>; }; + + /* + * Below are set of fixed, input clocks definitions, + * for which real frequencies have to be defined in board files. + * Those clocks can be used as reference clocks for some HW modules + * (as cpts, for example) by configuring corresponding clock muxes. + */ + tsipclka: tsipclka { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "tsipclka"; + }; + + tsipclkb: tsipclkb { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "tsipclkb"; + }; };