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[209.132.180.67]) by mx.google.com with ESMTP id r63si12737365plb.94.2019.04.02.17.19.29; Tue, 02 Apr 2019 17:19:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=U51JEyUA; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726130AbfDCAT3 (ORCPT + 7 others); Tue, 2 Apr 2019 20:19:29 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:39467 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725912AbfDCAT3 (ORCPT ); Tue, 2 Apr 2019 20:19:29 -0400 Received: by mail-pg1-f193.google.com with SMTP id k3so7358200pga.6 for ; Tue, 02 Apr 2019 17:19:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VLWHuNFSN049kn9QrMYQtND+EczALKS7lhqGdvg+Txc=; b=U51JEyUAGJR4daCgC6KKvAhEKulSH9UuAWldWiwR8b1WujX72Kulj/JCAW4tD2Wicx OQogoc+aoWNJD2ceFwxHFVXWerbhJjxyQW4L6ypseEEXED2syBE2g2ryimnk+6LgSRHx VVnzr3rqKkP5w6kNGjUtt1hQUUt/nFf5GkmsiHz4pDYOUFVtTJPp8vrJh4ZOd2ZGzZIN gV9vYM3J6nC0Dq3wsCkXTlBn9fPnKjJxRgPhth4wSt0t0AhqsCvXcP8fr+V3WoZ4SgYy vJWVJaSpDjEfu3DPgMBZowAeqO010lRzU0GGn6R9qti9dhs2tYaf3wFxSyWxSaYwrmk9 vm7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=VLWHuNFSN049kn9QrMYQtND+EczALKS7lhqGdvg+Txc=; b=DDZ88ku3pvzjFVzm6EoELctIXcaFLC/MjWy6NQa4qbXkesKgjpGdyUDKnVkxzi6nh/ UkkR+7Rv/RXsLh8q0h9A8TbjApy6PNALK2VqNqouKAJOgtfgEIZA9v+IPuAob79nbJbQ He3OGoxAPm6eGMevP1i+he1X1uhQluMbiq3ZN5XeRikLYnEPGGNXrEXz04a9YVj63FES e5Y3bTLc8AcFYpWuzRwthxsoLeS+oWJyCtrx0Uq3vMX2QkwRxBD35PpGy2pGtOSGzjYb vsL3O8j8itVVbZg7UY78NMNKAsZGr1lxV83AMprtcPDHE7039eNbOOqOBRvRhGtxufw2 l0dg== X-Gm-Message-State: APjAAAWy6VkkdNw2OqBozbAU68oL36ZTOZoKCacFphc8pOXd80X/ZGlH Yk43qMQT6qPxrrfa+etQAd8= X-Received: by 2002:a63:5c53:: with SMTP id n19mr4059055pgm.193.1554250768178; Tue, 02 Apr 2019 17:19:28 -0700 (PDT) Received: from voyager.jms.id.au ([36.255.48.244]) by smtp.gmail.com with ESMTPSA id p128sm32720594pfp.30.2019.04.02.17.19.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 02 Apr 2019 17:19:27 -0700 (PDT) Received: by voyager.jms.id.au (sSMTP sendmail emulation); Wed, 03 Apr 2019 10:49:20 +1030 From: Joel Stanley To: Daniel Vetter , Rob Herring Cc: David Airlie , Andrew Jeffery , Maarten Lankhorst , Sean Paul , linux-aspeed@lists.ozlabs.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Noralf_Tr=C3=B8nnes?= Subject: [PATCH v3 1/3] dt-bindings: gpu: Add ASPEED GFX bindings document Date: Wed, 3 Apr 2019 10:49:07 +1030 Message-Id: <20190403001909.31637-2-joel@jms.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403001909.31637-1-joel@jms.id.au> References: <20190403001909.31637-1-joel@jms.id.au> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This describes the ASPEED BMC SoC's display controller. Signed-off-by: Joel Stanley Reviewed-by: Andrew Jeffery --- v3: Add Andrew's reviewed-by .../devicetree/bindings/gpu/aspeed-gfx.txt | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpu/aspeed-gfx.txt -- 2.20.1 diff --git a/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt b/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt new file mode 100644 index 000000000000..a74033332668 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt @@ -0,0 +1,41 @@ +Device tree configuration for the GFX display deivce on the AST2500 SoCs. + +Required properties: + - compatible + * Must be one of the following: + + aspeed,ast2500-gfx + + aspeed,ast2400-gfx + * In addition, the ASPEED pinctrl bindings require the 'syscon' property to + be present + + - reg: Physical base address and length of the GFX registers + + - interrupts: interrupt number for the GFX device + + - clocks: clock number used to generate the pixel clock + + - resets: reset line that must be released to use the GFX device + + - memory-region: + Phandle to a memory region to allocate from, as defined in + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + + +Example: + +gfx: display@1e6e6000 { + compatible = "aspeed,ast2500-gfx", "syscon"; + reg = <0x1e6e6000 0x1000>; + reg-io-width = <4>; + clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; + resets = <&syscon ASPEED_RESET_CRT1>; + interrupts = <0x19>; + memory-region = <&gfx_memory>; +}; + +gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; +};