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[209.132.180.67]) by mx.google.com with ESMTP id d33si10298895pla.315.2019.04.01.19.19.53; Mon, 01 Apr 2019 19:19:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=gmM54o7t; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728623AbfDBCTw (ORCPT + 7 others); Mon, 1 Apr 2019 22:19:52 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:34893 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726269AbfDBCTw (ORCPT ); Mon, 1 Apr 2019 22:19:52 -0400 Received: by mail-pl1-f196.google.com with SMTP id p19so5441966plo.2 for ; Mon, 01 Apr 2019 19:19:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=omo+gsvUv/mNXteAzfVazNvpx4ZfEVnSExqzqZ2Pw8w=; b=gmM54o7tALuvzHXqk25AFF0tFlsGNM3AYaNl0ReZmOFwrNspYUu/+MS3AEVw7dKXcX CLzPZEZbh5lAFryM77GljMFdFTUaZ9l4TWdZFPxnnAdTWshwGcrWHnF93u85gVI9AuOl UaPfZK/0WkJAIKPHq2ifIToXKhGjdFcW1oMOdgUcvRizAZyUD9GPT6oQ8N5hyzcNlREq lqrB6s/HbEGX5tjiBBiqXh/nVc1Ji17JEqc/waxSolXe9HjBj7bFgs8+VY4WGNT3l2Tx vyKNtiQrwRHXmJobJJT+KaqekUmml6mx5L7R7PI0aN3PBP7P9roG2fnWMdprcd5RCork IwGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=omo+gsvUv/mNXteAzfVazNvpx4ZfEVnSExqzqZ2Pw8w=; b=RsF/6dz+N1e9v6cfWPRm6QXmsI12miZU7CLna061STjnV+P3yPHcx7caTYMld/WHt6 LL680qbbXG3hU9XJp4hLljE4XGCYjFMqImywPGK2f4TQk7QM/bXawzcMzbPhNRf1QBHf XmtM+IDOyGo9+x1ptDg8rUTPhbfFP8nNd67PIk/99emvipdfOMuixlyU/XHjz6vOZlWD SnRQrAhX8HCLciYg39pcOuHiut+rJmamU+b8kj+qhlVZ9rejQLLg63ZSEmWQs3Sy8l0W BxhLm4waxm3t3uTp+y+0R37PmfzrL9V7DCik37UJi5FqL+IGM1qu4RsCqRPZYFiL2vT4 8zvg== X-Gm-Message-State: APjAAAUDOdCULI3PjEV8s9zyuwy1wdjtyKUNOcg6XniorM+zs8zIR05X hJVgKfBgkmmkzLWsHTos/IY= X-Received: by 2002:a17:902:7b96:: with SMTP id w22mr33258498pll.28.1554171591786; Mon, 01 Apr 2019 19:19:51 -0700 (PDT) Received: from voyager.jms.id.au ([36.255.48.244]) by smtp.gmail.com with ESMTPSA id 26sm15918553pfj.93.2019.04.01.19.19.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 01 Apr 2019 19:19:51 -0700 (PDT) Received: by voyager.jms.id.au (sSMTP sendmail emulation); Tue, 02 Apr 2019 12:49:43 +1030 From: Joel Stanley To: Daniel Vetter , Rob Herring Cc: David Airlie , Andrew Jeffery , Maarten Lankhorst , Sean Paul , linux-aspeed@lists.ozlabs.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Noralf_Tr=C3=B8nnes?= Subject: [PATCH v2 1/3] dt-bindings: gpu: Add ASPEED GFX bindings document Date: Tue, 2 Apr 2019 12:49:31 +1030 Message-Id: <20190402021933.13071-2-joel@jms.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190402021933.13071-1-joel@jms.id.au> References: <20190402021933.13071-1-joel@jms.id.au> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This describes the ASPEED BMC SoC's display controller. Signed-off-by: Joel Stanley --- .../devicetree/bindings/gpu/aspeed-gfx.txt | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpu/aspeed-gfx.txt -- 2.20.1 Reviewed-by: Andrew Jeffery diff --git a/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt b/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt new file mode 100644 index 000000000000..a74033332668 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt @@ -0,0 +1,41 @@ +Device tree configuration for the GFX display deivce on the AST2500 SoCs. + +Required properties: + - compatible + * Must be one of the following: + + aspeed,ast2500-gfx + + aspeed,ast2400-gfx + * In addition, the ASPEED pinctrl bindings require the 'syscon' property to + be present + + - reg: Physical base address and length of the GFX registers + + - interrupts: interrupt number for the GFX device + + - clocks: clock number used to generate the pixel clock + + - resets: reset line that must be released to use the GFX device + + - memory-region: + Phandle to a memory region to allocate from, as defined in + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + + +Example: + +gfx: display@1e6e6000 { + compatible = "aspeed,ast2500-gfx", "syscon"; + reg = <0x1e6e6000 0x1000>; + reg-io-width = <4>; + clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; + resets = <&syscon ASPEED_RESET_CRT1>; + interrupts = <0x19>; + memory-region = <&gfx_memory>; +}; + +gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; +};