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[209.132.180.67]) by mx.google.com with ESMTP id x4si1996427pll.344.2019.03.27.22.43.51; Wed, 27 Mar 2019 22:43:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=VO4zQcBJ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725806AbfC1Fnv (ORCPT + 7 others); Thu, 28 Mar 2019 01:43:51 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:36558 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725765AbfC1Fnu (ORCPT ); Thu, 28 Mar 2019 01:43:50 -0400 Received: by mail-pg1-f193.google.com with SMTP id 85so45681pgc.3 for ; Wed, 27 Mar 2019 22:43:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=omo+gsvUv/mNXteAzfVazNvpx4ZfEVnSExqzqZ2Pw8w=; b=VO4zQcBJoyYsOZEF8Bnt6hjP18Lm/x1+VEFxpPb4hjjOVKulSiPNWs+bFEJKuyD76x +BfaMKLTPVCiCzK61evh+w35TtVsZDaCZeFfsuQs7cazgdT7vHD5Ejwb7OPV7YtYLgNk TQi0xeCWQB0rYrjYzHU8GTPN+7WyF6mMtigyz2Kr8fUv8G76a35oSa8p3T2T7pEzIAZ5 LMgG3vBQKD6wIwouqxhZJSuoiCrfHoVPWhDg40myK/6j6V3hMCGPFW7Ott/pgX7oDxiw p19NdmaxEhBun7rQYTUpfJ3EnHd68s3gv9KCK5PGGPJ0aMJhLrMAnDMvA9eJb/OpcpsX +TtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=omo+gsvUv/mNXteAzfVazNvpx4ZfEVnSExqzqZ2Pw8w=; b=NCYnNzKCJwND2osxldRoHxmzVs/HUBPcWqnMhagpRcFY9kG75fMjsDco4p1Mfcg2tf 3y0VBlh96khkq2Z7IPRpRbGuVZo3jSD2Co0/ddtXOtWJsdlH9oy4bBffN/504SXlx/fr sv2/zDOcVPEsAcPoB4kGD5MOwaI3D+iZSpDihABg24yTbXM+0ZcSoiVrEwZdlStnmaz5 012NSjl8zpL3qy25NsmYKg2isx+Wd2SOhpra2jQYEc3cLcmC5LZOnZKayclcJopk2sau I4ln7tGcwoYcMKs+eurh6qgpDmBCnHmCCgq9PegAzba+u2ommvNkc3ajnqStotD2J2ep b8Jg== X-Gm-Message-State: APjAAAWN4pOw59ctGJYa6kcDHBf5ie6RT6IvbAXvr1WXyT/GKnliWW6k jBzh/M8WM/w8LG+zgQrmtHI= X-Received: by 2002:a62:571b:: with SMTP id l27mr10945987pfb.195.1553751830061; Wed, 27 Mar 2019 22:43:50 -0700 (PDT) Received: from voyager.jms.id.au ([36.255.48.244]) by smtp.gmail.com with ESMTPSA id j24sm26595794pgl.58.2019.03.27.22.43.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Mar 2019 22:43:49 -0700 (PDT) Received: by voyager.jms.id.au (sSMTP sendmail emulation); Thu, 28 Mar 2019 16:13:41 +1030 From: Joel Stanley To: David Airlie , Daniel Vetter , Rob Herring Cc: Andrew Jeffery , Maarten Lankhorst , Maxime Ripard , Sean Paul , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org Subject: [PATCH 1/2] dt-bindings: gpu: Add ASPEED GFX bindings document Date: Thu, 28 Mar 2019 16:13:15 +1030 Message-Id: <20190328054316.17939-2-joel@jms.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190328054316.17939-1-joel@jms.id.au> References: <20190328054316.17939-1-joel@jms.id.au> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This describes the ASPEED BMC SoC's display controller. Signed-off-by: Joel Stanley --- .../devicetree/bindings/gpu/aspeed-gfx.txt | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpu/aspeed-gfx.txt -- 2.20.1 diff --git a/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt b/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt new file mode 100644 index 000000000000..a74033332668 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt @@ -0,0 +1,41 @@ +Device tree configuration for the GFX display deivce on the AST2500 SoCs. + +Required properties: + - compatible + * Must be one of the following: + + aspeed,ast2500-gfx + + aspeed,ast2400-gfx + * In addition, the ASPEED pinctrl bindings require the 'syscon' property to + be present + + - reg: Physical base address and length of the GFX registers + + - interrupts: interrupt number for the GFX device + + - clocks: clock number used to generate the pixel clock + + - resets: reset line that must be released to use the GFX device + + - memory-region: + Phandle to a memory region to allocate from, as defined in + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + + +Example: + +gfx: display@1e6e6000 { + compatible = "aspeed,ast2500-gfx", "syscon"; + reg = <0x1e6e6000 0x1000>; + reg-io-width = <4>; + clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; + resets = <&syscon ASPEED_RESET_CRT1>; + interrupts = <0x19>; + memory-region = <&gfx_memory>; +}; + +gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; +};