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[109.49.46.234]) by smtp.gmail.com with ESMTPSA id q63sm17958010wma.21.2019.03.26.04.02.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 Mar 2019 04:02:43 -0700 (PDT) From: Rui Miguel Silva To: Shawn Guo , Rob Herring , Fabio Estevam Cc: Laurent Pinchart , devicetree@vger.kernel.org, Rui Miguel Silva , Philipp Zabel Subject: [PATCH v2 2/5] ARM: dts: imx7s: add multiplexer controls Date: Tue, 26 Mar 2019 11:02:24 +0000 Message-Id: <20190326110227.7324-3-rui.silva@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190326110227.7324-1-rui.silva@linaro.org> References: <20190326110227.7324-1-rui.silva@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The IOMUXC General Purpose Register has bitfield to control video bus multiplexer to control the CSI input between the MIPI-CSI2 and parallel interface. Add that register and mask. Signed-off-by: Rui Miguel Silva Reviewed-by: Philipp Zabel --- arch/arm/boot/dts/imx7s.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) -- 2.21.0 diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 9a680d3d6424..792efcd2caa1 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -497,8 +497,15 @@ gpr: iomuxc-gpr@30340000 { compatible = "fsl,imx7d-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon"; + "fsl,imx6q-iomuxc-gpr", "syscon", + "simple-mfd"; reg = <0x30340000 0x10000>; + + mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <0>; + mux-reg-masks = <0x14 0x00000010>; + }; }; ocotp: ocotp-ctrl@30350000 {