From patchwork Mon Mar 25 08:34:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161032 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696207jan; Mon, 25 Mar 2019 01:36:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqxNxBTX9ntjWoWwo98XPUuyrA57hTh2wXQTYE8IkWPne3wjeBh+K0Egf8SUImchWva0894O X-Received: by 2002:a65:6389:: with SMTP id h9mr4245614pgv.398.1553503006140; Mon, 25 Mar 2019 01:36:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503006; cv=none; d=google.com; s=arc-20160816; b=WEmj1b4Y9xX05Mqu80c0tZrwjxvT2ecinrdh/j33hqmVXtMMXhmq0u1kqCyWAbvMus rtt1busyAIC3Zc+WMjmQEiBo6azbiFfwaKA40Xi7OqAFlZfEc10SU8qUE/HGdMBV1s9J u41UqtK9Grn3AWeOzCRuY0P07Wh4SVL5/yQPfoOKBlJwJX3fKrEud4YncYD/GVbt0cLZ OkzBji3+si6MAKSFT/t1cXtPiSmvnQUq5k49vqFR0vaIFWfZfEAg8+0O8/OFA2mBB7gU IxsHKy/Js5n2xQMi44Gp+6Nh4vZDz007EjpZfp7RzxFEK/TsUMkTkTQuMyUHkNNQhNRV /maQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Wx7Yx/QA57xsICcriJ4mx2XFfp/NPcRkGKsQ4ow3LF0=; b=pvp5yvCxiBMGxvQ9y2rS6JYc+A2Fd+IzEL3ZvhIKqygHQjJEc6ACXMug3tSNC/L6OV Dq2xPUP5J4hXi9QVkpLYCVjIwN8GDZw9Lcnu74beNYN/E+S11/jsh0Fmg/m9aeuLsxz5 5GizlTxAlpZ0RKi1A5g2TtteofCEgjz+2xEW8+xbc4UncjaTnRSmBD3Gne/aA6WiKeIE /j6oQex2Xw7uG+Fr4IaBo9tquWkcOU5HVcq9aInV7iHiv50yfls5TKK/SOKggFajKdI1 wqrFeub/0aaEdowMWF+hs79ir4cVTmu2RNdytuRVWa11G+s1yMMbQwhihhEWrIeIQT9L I8kA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RpZhgdcI; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l4si12082288pgp.169.2019.03.25.01.36.45; Mon, 25 Mar 2019 01:36:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RpZhgdcI; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730198AbfCYIgo (ORCPT + 7 others); Mon, 25 Mar 2019 04:36:44 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:33866 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730175AbfCYIgo (ORCPT ); Mon, 25 Mar 2019 04:36:44 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8aOK1030728; Mon, 25 Mar 2019 03:36:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553502984; bh=Wx7Yx/QA57xsICcriJ4mx2XFfp/NPcRkGKsQ4ow3LF0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RpZhgdcIh9GESuhQjBLGrARoKFT8uLTABCPEPOcNeym31O19xBQdDs0YyXtrCisSR HK8VqUPJ8LfL/fbxiL8Nj4sW17IDxP5DD7Fmh8HcCPBLUQhfJf/fGed1y3qw/WLlcg /XSuo88ewHWFIHeJBXKei7ChA9XVSYTDg+FoZ6Ow= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8aODI088620 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:36:24 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:36:24 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:36:24 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsFm006534; Mon, 25 Mar 2019 03:36:20 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 06/26] PCI: keystone: Move initializations to appropriate places Date: Mon, 25 Mar 2019 14:04:41 +0530 Message-ID: <20190325083501.8088-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org No functional change. Move host specific platform_get_resource to ks_add_pcie_port and the common platform_get_resource (applicable to both host and endpoint) to probe. This is in preparation for adding endpoint support to pci-keystone driver. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 27 +++++++++++++---------- 1 file changed, 15 insertions(+), 12 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 5eebef9b9ada..95997885a05c 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -806,11 +806,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, struct resource *res; int ret; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); - pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pci->dbi_base)) - return PTR_ERR(pci->dbi_base); - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); if (IS_ERR(pp->va_cfg0_base)) @@ -818,13 +813,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, pp->va_cfg1_base = pp->va_cfg0_base; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); - ks_pcie->va_app_base = devm_ioremap_resource(dev, res); - if (IS_ERR(ks_pcie->va_app_base)) - return PTR_ERR(ks_pcie->va_app_base); - - ks_pcie->app = *res; - pp->ops = &ks_pcie_host_ops; ret = dw_pcie_host_init(pp); if (ret) { @@ -895,6 +883,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct keystone_pcie *ks_pcie; struct device_link **link; + struct resource *res; + void __iomem *base; u32 num_viewport; struct phy **phy; u32 num_lanes; @@ -911,6 +901,19 @@ static int __init ks_pcie_probe(struct platform_device *pdev) if (!pci) return -ENOMEM; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); + ks_pcie->va_app_base = devm_ioremap_resource(dev, res); + if (IS_ERR(ks_pcie->va_app_base)) + return PTR_ERR(ks_pcie->va_app_base); + + ks_pcie->app = *res; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); + base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + pci->dbi_base = base; pci->dev = dev; pci->ops = &ks_pcie_dw_pcie_ops;