From patchwork Mon Mar 25 08:34:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161043 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696902jan; Mon, 25 Mar 2019 01:37:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqzV0SIHcWGK2DglVFa6k7OUMKArgK+aXccgTJwMPq5KuaJCoScS8UPs8XpW95HjxZgnZZxX X-Received: by 2002:a17:902:9a0b:: with SMTP id v11mr23919851plp.194.1553503060510; Mon, 25 Mar 2019 01:37:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503060; cv=none; d=google.com; s=arc-20160816; b=l+RzsQfUGUbAltmTmKhSodviushbbc0VkwQeAiFCrI7cuRvzcSqzL//zJLZFA5C8Us rLH0NzfsJzwv4lyT4oqj8AXiDgakiAt9xRXWO9+kYCp534KoKvwKfcfKf224QMSVsCkS zwumb5OhUAnwW64OIvc9+gldi/XV1mIc3pLv8XcmPcyw2XSyH2DpugqkX6WcRdCHGy5F 6t7xjqENHDIgLusneTZeSHJ03g1uMY2fTb5dmxseHL5Q5f53zXdMLPJMVhch4xzupWIN m5EMOo6bV5sj4Uj2gk7RP7yByX1OiHnNKKXuPSljatg5RtdvVYjzgtDoTzvzrZ5xcJBH 0kmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=F1vNw6974A4SxeLsowTyiNZ0yV33iVQDSJNdrli8b/8=; b=jq2J5c3ygpXS0auqCeNEarDgEwFdjIRXXi+fBWgX8rAtdznUrJahTEndpzIZ83x79Z tNG7/Qm+Re5PdRGFTmfQm+6OvB9TmyTOrCbpqtVBeBnu1Bzin36Y0c2LQs1CyC0iyT9R OP+l3CpjStpKRfXIf5KAxYUApup1vMSsDhL8766rj2wTzpDaudf3bP4aAS1Ddg1819FI k7SqYpFYcE0Z1I8qIeKK23/3N+ZrWxr5yONz2FTLn24rur2wgOPfQpSJE1IkdIr/WBSf uMYaUyNhptRMErhNpRZnuBTG356eU4ztTu+1cEU4rCxt2XuZ0dJpYGS8O++6g/R9EqQy Fk9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=y3kNCOz8; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 16si13502314pga.351.2019.03.25.01.37.40; Mon, 25 Mar 2019 01:37:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=y3kNCOz8; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730369AbfCYIhj (ORCPT + 7 others); Mon, 25 Mar 2019 04:37:39 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:54964 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729929AbfCYIhi (ORCPT ); Mon, 25 Mar 2019 04:37:38 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8bOBu106956; Mon, 25 Mar 2019 03:37:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553503044; bh=F1vNw6974A4SxeLsowTyiNZ0yV33iVQDSJNdrli8b/8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=y3kNCOz8dBIRp1kJky4rjbnokoiNeMhg9+CX8D4GZ3jb/M1ISn0gUgVyujyYT0E6t 25GX4h/rYcc/ioIfebB/cBLCBCIwRL3PCKN8DtoB2wWHVLjx3fwOAEXoP+5sJIJ5ID 3ohoWPVJxiWiNHx6TCJUTJ+vKCoh+6WC0EYGFuxU= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8bOqM017802 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:37:24 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:37:23 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:37:24 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsG2006534; Mon, 25 Mar 2019 03:37:20 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 20/26] PCI: dwc: Fix dw_pcie_ep_find_capability to return correct capability offset Date: Mon, 25 Mar 2019 14:04:55 +0530 Message-ID: <20190325083501.8088-21-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org commit beb4641a787df79a ("PCI: dwc: Add MSI-X callbacks handler") while adding MSI-X callback handler, introduced dw_pcie_ep_find_capability and __dw_pcie_ep_find_next_cap for finding the MSI and MSIX capability. However if MSI or MSIX capability is the last capability (i.e there are no additional items in the capabilities list and the Next Capability Pointer is set to '0'), __dw_pcie_ep_find_next_cap will return '0' even though MSI or MSIX capability may be present. This is because of incorrect ordering of "next_cap_ptr" check. Fix it here. Fixes: beb4641a787df79a142 ("PCI: dwc: Add MSI-X callbacks handler") Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-ep.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index dc6a4bbd3ace..74477ad7467f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -46,16 +46,19 @@ static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, u8 cap_id, next_cap_ptr; u16 reg; + if (!cap_ptr) + return 0; + reg = dw_pcie_readw_dbi(pci, cap_ptr); - next_cap_ptr = (reg & 0xff00) >> 8; cap_id = (reg & 0x00ff); - if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX) + if (cap_id > PCI_CAP_ID_MAX) return 0; if (cap_id == cap) return cap_ptr; + next_cap_ptr = (reg & 0xff00) >> 8; return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); } @@ -67,9 +70,6 @@ static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap) reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); next_cap_ptr = (reg & 0x00ff); - if (!next_cap_ptr) - return 0; - return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); }