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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id m73sm1316965lfa.65.2019.02.21.07.45.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Feb 2019 07:45:41 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Linus Walleij , devicetree@vger.kernel.org, Bartosz Golaszewski , Rob Herring Subject: [PATCH 13/30 v2] gpio: ixp4xx: Add DT bindings Date: Thu, 21 Feb 2019 16:44:41 +0100 Message-Id: <20190221154458.23763-14-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190221154458.23763-1-linus.walleij@linaro.org> References: <20190221154458.23763-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds DT bindings for the IXP4xx GPIO controller. Cc: devicetree@vger.kernel.org Reviewed-by: Bartosz Golaszewski Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Collect Bartosz and Rob's review tags. --- .../bindings/gpio/intel,ixp4xx-gpio.txt | 38 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt -- 2.20.1 diff --git a/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt new file mode 100644 index 000000000000..8dc41ed99685 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt @@ -0,0 +1,38 @@ +Intel IXP4xx XScale Networking Processors GPIO + +This GPIO controller is found in the Intel IXP4xx processors. +It supports 16 GPIO lines. + +The interrupt portions of the GPIO controller is hierarchical: +the synchronous edge detector is part of the GPIO block, but the +actual enabling/disabling of the interrupt line is done in the +main IXP4xx interrupt controller which has a 1:1 mapping for +the first 12 GPIO lines to 12 system interrupts. + +The remaining 4 GPIO lines can not be used for receiving +interrupts. + +The interrupt parent of this GPIO controller must be the +IXP4xx interrupt controller. + +Required properties: + +- compatible : Should be + "intel,ixp4xx-gpio" +- reg : Should contain registers location and length +- gpio-controller : marks this as a GPIO controller +- #gpio-cells : Should be 2, see gpio/gpio.txt +- interrupt-controller : marks this as an interrupt controller +- #interrupt-cells : a standard two-cell interrupt, see + interrupt-controller/interrupts.txt + +Example: + +gpio0: gpio@c8004000 { + compatible = "intel,ixp4xx-gpio"; + reg = <0xc8004000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; +}; diff --git a/MAINTAINERS b/MAINTAINERS index bd04142b1026..b44ee076d57c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1650,6 +1650,7 @@ M: Imre Kaloz M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml F: arch/arm/mach-ixp4xx/