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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id 85-v6sm2456868lja.16.2019.02.03.13.42.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 03 Feb 2019 13:42:38 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Tim Harvey , Arnd Bergmann , Olof Johansson , Linus Walleij , Marc Zyngier , Jason Cooper , Thomas Gleixner , devicetree@vger.kernel.org Subject: [PATCH 09/17 v1] irqchip: ixp4xx: Add DT bindings Date: Sun, 3 Feb 2019 22:41:57 +0100 Message-Id: <20190203214205.13594-10-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190203214205.13594-1-linus.walleij@linaro.org> References: <20190203214205.13594-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the IXP4xx interrupt controller. It's a standard 2-cell controller. Cc: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- irqchip maintainers: I am requesting an ACK for this once you're happy with the bindings, as I intend to merge all of this IXP4xx rework through ARM SoC. --- .../intel,ixp4xx-interrupt.txt | 33 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt -- 2.20.1 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt new file mode 100644 index 000000000000..70ee93b9a6c0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt @@ -0,0 +1,33 @@ +* Intel IXP4xx XScale Networking Processors Interrupt Controller + +This interrupt controller is found in the Intel IXP4xx processors. +Some processors have 32 interrupts, some have up to 64 interrupts. +The exact number of interrupts is determined from the compatible +string. + +The distinct IXP4xx families with different interrupt controller +variations are IXP42x, IXP43x, IXP45x and IXP46x. Those four +families were the only ones to reach the developer and consumer +market. + +Required properties: +- compatible: must be one of + "intel,ixp42x-interrupt" + "intel,ixp43x-interrupt" + "intel,ixp45x-interrupt" + "intel,ixp46x-interrupt" +- reg: The register bank for the interrupt controller. +- interrupt-controller: Identifies the node as an interrupt controller +- #interrupt-cells: The number of cells to define the interrupts. + Must be <2>. The bindings follows the standard binding for controllers + with two cells specified in + interrupt-controller/interrupts.txt + +Example: + +intcon: interrupt-controller@c8003000 { + compatible = "intel,ixp43x-interrupt"; + reg = <0xc8003000 0x100>; + interrupt-controller; + #interrupt-cells = <2>; +}; diff --git a/MAINTAINERS b/MAINTAINERS index a2fb67b75026..ec318f09540c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1650,6 +1650,7 @@ M: Imre Kaloz M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt F: arch/arm/mach-ixp4xx/ F: drivers/clocksource/timer-ixp4xx.c F: drivers/gpio/gpio-ixp4xx.c