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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id k15sm4357928pfb.147.2019.01.30.16.40.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Jan 2019 16:40:02 -0800 (PST) From: Bjorn Andersson To: Andy Gross , David Brown Cc: Rob Herring , Mark Rutland , Ohad Ben-Cohen , Arun Kumar Neelakantam , Sibi Sankar , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org Subject: [PATCH v5 09/10] arm64: dts: qcom: Add AOSS QMP node Date: Wed, 30 Jan 2019 16:39:32 -0800 Message-Id: <20190131003933.11436-10-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190131003933.11436-1-bjorn.andersson@linaro.org> References: <20190131003933.11436-1-bjorn.andersson@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The AOSS QMP provides a number of power domains, used for QDSS and PIL, add the node for this. Signed-off-by: Bjorn Andersson --- Changes since v4: - None Changes since v3: - None arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 07d9cd6fba7d..dc43fee8bb90 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -2076,6 +2077,15 @@ #reset-cells = <1>; }; + aoss_qmp: qmp@c300000 { + compatible = "qcom,sdm845-aoss-qmp"; + reg = <0 0x0c300000 0 0x100000>; + interrupts = ; + mboxes = <&apss_shared 0>; + + #power-domain-cells = <1>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>,